CODEWITHSUNDEEP
vhdl
Aya Ismail
Aya Ismail

Reputation: 11

What is the difference between signed and unsigned addition in vhdl?

If I add two signed numbers like -1 and -1 the result should be -2. If I add the same values but as unsigned the output will be the same.

So what's the difference between signed and unsigned?

Upvotes: 1

Views: 9172

Answers (2)

Jonathan Drolet
Jonathan Drolet

Reputation: 3388

This is perfectly normal, addition in 2's complement is logically the same whether the operands are signed or unsigned. Your interpretation of the value will differ though.

The major difference between the two types is how the vectors are extended to larger value. An unsigned is always extended with leading zeros, while a signed is extended with the sign bit (msb).

For example:

signal a_u : unsigned(11 downto 0);
signal b_u : unsigned( 1 downto 0);
signal c_u : unsigned(11 downto 0);
signal a_s :   signed(11 downto 0);
signal b_s :   signed( 1 downto 0);
signal c_s :   signed(11 downto 0);
...
a_u <= X"123";
b_u <= "11"; -- 3
c_u <= a_u + b_u; -- b_u is extended to 12 bits with 0, result is X"126"
a_s <= X"123";
b_s <= "11"; -- -1
c_s <= a_s + b_s; -- b_s is extended with sign bit (1), result is X"122";

Upvotes: 2

trazillian
trazillian

Reputation: 144

In general: SIGNED and UNSIGNED types are provided in the std_logic_arith, numeric_std, and numeric_bit packages in the ieee library.

UNSIGNED types represent unsigned numerical values, which can be positive or zero only. The Compiler interprets each UNSIGNED type as a binary number, with the digit on the left as the MSB

SIGNED types represent signed numerical values, which can be positive, zero, or negative. The Compiler interprets each SIGNED type as a two's complement binary representation; the leftmost bit indicates whether the value is positive or negative

So there might be something wrong in your code..

Upvotes: 0

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