CODEWITHSUNDEEP
vhdl
NjN
NjN

Reputation: 27

Unsigned operation need signed variable or what in VHDL

I am facing an problem ...in which p3,p6,p9 ,p1,p4 p7 are 8 bit std_logic_vector.

I want to do operation like (p3+2*p6+p9)-(p1+2*p4+p7) without multipier but by shift operation.(by two=>left shift by 1) and its result may be + or -ve.

so I want signed one.if it is more than 255 make the result 255 other wise what ever the 8 bit value. The first h1 is giving wrong result.

Below you find the code

-

- Company: 
-- Engineer: 
-- 
-- Create Date:    21:01:45 01/11/2013 
-- Design Name: 
-- Module Name:    HRZ - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HRZ is
PORT ( CLK     : IN  STD_LOGIC;
             RST     : IN  STD_LOGIC;
             P1,P3,P4,P6,P7,P9 : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
             MAG_HRZ : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0) );
end HRZ;

architecture Behavioral of HRZ is
SIGNAL H1: signed(17 DOWNTO 0) ;

SIGNAL THRESHOLD: signed(17 DOWNTO 0):="000000000011111111";
begin
P :  PROCESS(CLK)

BEGIN

H1<=SIGNED(('0'&P3+'0'&P6(7 DOWNTO 0)&'0'+'0'&P9)-('0'&P1+'0'&P4(7 DOWNTO 0)&'0'+'0'&P7));
IF(H1>=THRESHOLD) THEN
MAG_HRZ<="11111111";
ELSE
 IF H1(17)='0' THEN
  MAG_HRZ<=H1(7)&H1(6)&H1(5)&H1(4)&H1(3)&H1(2)&H1(1)&H1(0);
  ELSE
 MAG_HRZ<=NOT(H1(7)&H1(6)&H1(5)&H1(4)&H1(3)&H1(2)&H1(1)&H1(0))+'1';

  END IF;
END IF;
END PROCESS P;
end Behavioral;
vh

Upvotes: 0

Views: 942

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16832

I'd use integers, life is much easier then... constrain the inputs:

variable p1,p2,... : integer range 0 to 255;

your two intermediate values are also unsigned (or natural in the integer world):

variable i1, i2 : natural;

i1 := p3 + p6*2 + p9;
i2 := p1 + p4*2 + p7;

the final value needs to be a signed value, so of integer type:

variable final : integer;

final := i1 - i2;

This isn't the 80s, synthesisers are pretty smart - let the synthesiser figure it out. And "fire it" if

  • it doesn't just put a bit-shift in for the *2
  • it doesn't reduce the range of final to the right number of bits, as it ought to work out how many bits are required. Even so, the mapper will probably figure it out later anyway and optimise the unneeded bits away

Upvotes: 0

andrsmllr
andrsmllr

Reputation: 1223

Using the libs IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED is considered deprecated. You should use IEEE.NUMERIC_STD instead.
Besides from that, I think you do not need to give the explicit range P4(7 downto 0), P4 should do just fine. Same goes for P6.
I didn't test it, but try SIGNED('0'&(('0'&P3+'0'&P6&'0'+'0'&P9)-('0'&P1+'0'&P4&'0'+'0'&P7)));. I think the problem here is the sign extension when converting to signed, so adding an additional zero at the front should fix it.

Upvotes: 1

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