CODEWITHSUNDEEP
vhdl
Jim Bob
Jim Bob

Reputation: 82

How can I index into a vhdl std_logic_vector?

I have the following declarations:

signal count:STD_LOGIC_VECTOR (3 downto 0);
signal txbuff:STD_LOGIC_VECTOR (7 downto 0);
  1. dout is a std_logic output
  2. I am using IEEE.NUMERIC_STD.ALL;

I want to use the vector count as an index into txbuff. Among the many things I've tried is the following:

count<=std_logic_vector(unsigned(count)-1);
dout<=txbuff(unsigned(count));

but I get the following error:

Line 99. Wrong index type for txbuff.

Upvotes: 4

Views: 26306

Answers (3)

user1818839
user1818839

Reputation:

You need an integer as the index type. (Or with other arrays, you can use any discrete type, such as as enumeration).

Other answers have showed you how to get there using type conversion functions : I'll ask instead, why not make "count" an integer, like natural range 0 to 15 in the first place? It'll synthesise just the same, and make for cleaner simpler code.

Upvotes: 5

user2534517
user2534517

Reputation: 41

You need to convert to integer using the to_integer function. Check the parameterised MUX:

architecture RTL of MUX is
begin
  -----------------------------------------------------------------------
  -- MUX_RTL
  -----------------------------------------------------------------------
  -- Implements a multiplexer
  -----------------------------------------------------------------------
  MUX_RTL: process(DATA_IN, ADDR_IN)
    variable ADDR_IN_INT : integer range 0 to 2**ADDR_WIDTH-1; -- holds the integer value of the address
  begin
    ADDR_IN_INT := to_integer(unsigned(ADDR_IN));
    DATA_OUT <= DATA_IN(ADDR_IN_INT);
  end process MUX_RTL;
end architecture RTL;

Upvotes: 1

Bill Lynch
Bill Lynch

Reputation: 81926

We actually want to convert the number to an integer, not an unsigned or signed.

To do this, we can use to_integer as defined in numeric_std. Here's an example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

entity conv_test is Port (
    data_in  : in std_logic_vector(7 downto 0);
    data_sel : in std_logic_vector(2 downto 0);
    data_out : out std_logic
);
end conv_test;

architecture Behavioral of conv_test is
begin
    data_out <= data_out(to_integer(unsigned(data_sel)));
end Behavioral;

Upvotes: 3

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