CODEWITHSUNDEEP
verilog
Rol
Rol

Reputation: 209

Inertial delay in Verilog HDL

I found two different sources that explain inertial delay in Verilog HDL in two different ways.

1) The first one says that any input signal shorter than the specified delay will be ignored.

2) The second one says that, given a change at one of the inputs, the output signal will be evaluated at the scheduled time using the values of the input signal at that time.

For example: Consider a delayed buffer

assign #4 out = in;
initial
  begin
    in = 0;
 #5 in = 1;
 #1 in = 0;
 #1 in = 1;
  end

If we monitor the signals, this would result in

     0         5  6  7  8  9 10 11  
     |         |  |  |  |  |  |  |   
                __    _________________
in    _________|  |__|
                                  _____
out1) XXXXXXX____________________|
                            ___________
out2) XXXXXXX______________|

out1) ignored the input (5,6) pulse in "up" and the (6,7) pulse in "down" state for being too short in time, only 1 time unit. But then "in" stayed up long enough (7,11) and thus out changed at 11.

out2) scheduled an evaluation at time step 9, because the input changed at time 5. Similarly at times 10 and 11 for "in" having changed at times 6 and 7 respectively. So, at times 9, 10 and 11, "out" takes the current value of "in" at these times, which is always "up" in this case.

Which evaluation is the right one?

Upvotes: 4

Views: 13289

Answers (2)

Pulimon
Pulimon

Reputation: 1816

I would suggest you to look at the following links to get a good idea of how to implement inertial delay and transport delay in Verilog:

pdf_1

pdf_2

Upvotes: 1

Qiu
Qiu

Reputation: 5751

The easiest way to find out - test it. Let's add a simple line:

$monitor("%g out = %b", $time, out);

to monitor out signal and run some simulator (e.g. Riviera). The result will be:

 0 out = x
 4 out = 0
11 out = 1

So your first approach is the correct one.

Upvotes: 4

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