CODEWITHSUNDEEP
veriloghdl
user478571
user478571

Reputation:

? time delay, when using === or <=

When we use 

input reg [7:0] ast, f_out;

ast === f_out ;

ast <= ast + 8'b00000001;

for those operations " === and <= ", Have any time delay been occurred ?

EDIT: I think something small like 1 unit time, am I wrong ?

used language : verilog

Upvotes: 0

Views: 176

Answers (2)

toolic
toolic

Reputation: 62064

Time delays are most commonly specified using #. Since I see no # in your code, there is probably no delay.

Another way to add delays is to use a specify block, and you don't show that either. There are plenty of examples of specify in the Verilog IEEE Std.

You can check for delays yourself by running a simulation and printing time values:

$display($time);

Upvotes: 1

Marty
Marty

Reputation: 6654

There will be a simulation cycle delay if you use <= - ie a nonblocking assignment. Read up on blocking vs nonblocking assignments.

Also, === is not an assignment - its an equality operator that doesn't treat x and z as don't cares

Upvotes: 1

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