CODEWITHSUNDEEP
matlabvhdlxilinx-iseblack-box
Marie
Marie

Reputation: 1

Error in blackbox xilinx system generator

I use Xilinx system generator blocks in Matlab and i find the block black box wich can generate and simulate vhdl code. I programme a simple program in vhdl for port and,

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: name, inputs, outputs
entity andGate is                   
   port( A, B : in std_logic;
            F : out std_logic);
end andGate;

--FUNCTIONAL DESCRIPTION: how the AND Gate works
architecture func of andGate is 
begin
  F <= A and B;     
end func;

I simulate in xilinx with blackbox and i make simulation mode ISE Simulator because i use xilinx .

I apreciate any kind of help thanks :)

Upvotes: 0

Views: 898

Answers (1)

Serwan Bamerni
Serwan Bamerni

Reputation: 78

check your gateway in, you should select its output as Boolean

also, check the sampling time of the system, you should make all equal to 1

Upvotes: 0

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