CODEWITHSUNDEEP
system-verilog
Jan Bartels
Jan Bartels

Reputation: 348

How to pass a class between two modules?

I have two modules and a class and I would like to move that class from one module to the other. Something like this:

class foo;
   int x;
   int y;
endclass

module mod_A(output foo foo_inst, output event trig);
   initial begin
      foo my_foo = new;
      my_foo.x = 1;
      my_foo.y = 2;
      foo_inst = my_foo;
      ->trig;
   end
endmodule

module mod_B(input foo foo_inst, input event trig);
   always @(trig) begin
       $display("%d%d, is a funky number.", foo_inst.x, foo_inst.y);
   end
endmodule

module top();
   event trig;
   foo   foo_inst;
   mod_A mod_A(.trig, .foo_inst);
   mod_B mod_B(.trig, .foo_inst);
endmodule

Of course there're also some functions defined in the class which are used in each module. The issue with this setup is that I'm seeing errors for each ports of mod_B:

Error-[RIPLIP] Register in low conn of input port
Non-net variable 'foo_inst' cannot be an input or inout port.
Non-net variable   'trig'   cannot be an input or inout port.

EDAplayground does not support class objects as module ports and 1800-2012 only mentions interface declarations, events, arrays structures or unions in Port declarations (23.2.2) so my questions are:

Upvotes: 4

Views: 4196

Answers (1)

dave_59
dave_59

Reputation: 42738

A variable of any type can be an input or output port. You might have to write for your compiler 

input var foo foo_inst,

But it would be better to use a ref when a port is really a handle. 

module mod_A(ref foo foo_inst, ref event trig);

Note that you have a typo with foo_o or foo_inst and a race condition between a trigger ->trig and an event control @(trig).

Upvotes: 2

Related Questions