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verilogsystem-verilog
Electronics Wizzter
Electronics Wizzter

Reputation: 111

How to link output of a module to the input of another in System Verilog

Im not quite sure how to make a module which allows the output(B) of one module to become the input of another module(C).

Upvotes: 1

Views: 4844

Answers (1)

Serge
Serge

Reputation: 12384

1) you need to declare your modules with input and output ports

 module A(input clk, input sig, output out);
          .. do somethign here
 endmodule

 module B(input clk, output val);
         ... do something to generate val.
 endmodule

2) you would need to create a hierarchy of instances, instantiating those modules, inside a top-level one. The latter will declare wires which should be used to connect these two:

module top(output topout);
  wire clk;
  wire sig;
  wire out;

  A a(clk, sig, topout);
  B b(clk, sig);
endmodule

So, in the above example output port val of instance b of module B is assigned to the wire sig of the top-level module. The same wire sig is connected to the input port sig of the instance a of the module A.

The output port out of the insance a is also connected to the output port topout port of the top-level module.

in both cases the clk wire is connected to two input ports: instance a and instance b.

This is the basic idea.

Upvotes: 3

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