CODEWITHSUNDEEP
moduleverilog
Swayam Prabha
Swayam Prabha

Reputation: 25

Calling one module from another

I am trying to call one of the 2 modules (fifo_test_1 or fifo_test_2) depending on the value of bit data[0] in the following Verilog code.

module VC_selector(data);

  input [10:0] data;

  always @ (data[0])
  begin
    if(~data[0])
    begin
      fifo_test_1 t1(.buf_in(data));
    end
    else if (data[0])
    begin
      fifo_test_2 t2 (.buf_in(data));
    end
  end
endmodule

fifo_test_1 and fifo_test_2 modules are working fine. But the above code gives these errors:

** Error: C:/Users/Swayam/Documents/VC_selector.v(8): Undefined variable: fifo_test_1.
** Error: C:/Users/Swayam/Documents/VC_selector.v(8): near "t1": syntax error, unexpected IDENTIFIER
** Error: C:/Users/Swayam/Documents/VC_selector.v(12): Undefined variable: fifo_test_2.
** Error: C:/Users/Swayam/Documents/VC_selector.v(12): near "t2": syntax error, unexpected IDENTIFIER

Please help me debug the code.

Upvotes: 0

Views: 1506

Answers (1)

Strikeskids
Strikeskids

Reputation: 4052

You cannot change the modules included while the hardware is running. The modules must be a constant during execution. For that reason, you can't include a module definition inside an always statement.

One thing you could do is move the two modules outside the always block and use some logic to switch between their outputs. Because neither of the fifo modules have outputs that would be rather difficult to do in this particular case, but it is possible in the general case.

assign my_switched_output = data[0] ? module_1_output : module_2_output;

The ternary operator (used here) allows you to do this switching that it appears you are attempting to do.

Another thing to make sure you have done is to include both the module file you are trying to simulate/synthesize AND all of the submodule verilog files you need in the command. How to include all of these files based on the simulator.

Upvotes: 2

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