CODEWITHSUNDEEP
function
Swayam Prabha
Swayam Prabha

Reputation: 25

Calling function from another module in Verilog

I am trying to instantiate and use a function that has been defined in another module.

module simple_function();
function  myfunction;
input a, b, c, d;
begin
   myfunction = ((a+b) + (c-d));
end
endfunction
endmodule

 module  function_calling(a, b, c, d, e, f);                   
 input a, b, c, d, e ;
 output f;
 wire f;
 `include "myfunction.v" 
 assign f =  (myfunction (a,b,c,d)) ? e :0;
 endmodule

I got this code from http://www.asic-world.com/verilog/task_func1.html However, when I execute the same in ModelSim Altera Starter Edition 10.0d, I get this error:

  Cannot open `include file "myfunction.v".

Where am I going wrong?

Upvotes: 2

Views: 9680

Answers (2)

Azharuddin Saifi
Azharuddin Saifi

Reputation: 19

Another way for calling a function of one module into another module is through interface. You can pass interface ports into first module due to which interface will get the all functions and tasks into it, and then interface can be pass into second module, in this way second module can get tasks and functions of first module.

Upvotes: -1

Kaleb Droskiewicz
Kaleb Droskiewicz

Reputation: 90

An include directive has the same effect as copying and pasting that code in the same spot. From your code it looks like you are trying to define a module (simple_function) inside of another module (function_calling), which is not allowed.

Your function does not need to be contained inside a module. You should change myfunction.v to just contain the myfunction definition and remove the simple_function module entirely. That way when myfunction.v is included it has the same effect as the function being declared in function_calling.

Upvotes: 2

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