CODEWITHSUNDEEP
vhdlram
Daniil
Daniil

Reputation: 23

Array of 1-bit-wide memory

I'm using ISE 14.7 and i'm trying to create design with some 1-bit-wide distributed RAM blocks.

My memory declaration:

type tyMemory is array (0 to MEMORY_NUM - 1) of std_logic_vector(MEMORY_SIZE - 1 downto 0) ;
signal Memory: tyMemory := ( others => (others => '0')) ;
attribute ram_style : string ;
attribute ram_style of Memory : signal is "distributed" ;

My code:

MemoryGen : for i in 0 to MEMORY_NUM - 1 generate
    process( CLK )
    begin
        if rising_edge(CLK) then
            if CE = '1' then
                DataOut(i) <= Memory(i)(Addr(i)) ;
                Memory(i)(Addr(i)) <= DataIn(i) ;
            end if ;
        end if ;
    end process ; 
end generate ;

After synthesis i get this warning:

WARNING:Xst:3012 - Available block RAM resources offer a maximum of two write ports. 
You are apparently describing a RAM with 16 separate write ports for signal <Memory>. 
The RAM will be expanded on registers.

How can i forse xst to use distributed memory blocks with size=ARRAY_LENGTH and width=1?

I can create and use separate memory component(and is works), but i need more elegant solution.

Upvotes: 2

Views: 427

Answers (2)

Paebbels
Paebbels

Reputation: 16221

This should inferre 16 one bit wide BlockRAMs:

architecture ...
  attribute ram_style : string;

  subtype tyMemory is std_logic_vector(MEMORY_SIZE - 1 downto 0) ;

begin
  genMem : for i in 0 to MEMORY_NUM - 1 generate
    signal Memory : tyMemory := (others => '0');
    attribute ram_style of Memory : signal is "block";
  begin
    process(clk)
    begin
      if rising_edge(clk) then
        if CE = '1' then
          Memory(Addr(i)) <= DataIn(i) ;
          DataOut(i) <= Memory(Addr(i)) ;
        end if ;
      end if ;
    end process ; 
  end generate ;
end architecture;

Upvotes: 0

scary_jeff
scary_jeff

Reputation: 4374

You need to create an entity that describes a variable length 1-bit wide memory, then use a generate statement to create an array of these. While what you have done would provide the functionality you are asking for in a simulator, most FPGA tools will only extract memory elements if your code is written in certain ways.

You can find documentation on what code Xilinx ISE tools will understand as a memory element by selecting the appropriate document for your device here http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ise_n_xst_user_guide_v6s6.htm . Look under 'HDL Coding techniques'.

Note that if your memory length is large, you will not be able to get maximum performance from it without adding manual pipelining. I think you will get a synthesis message if your memory exceeds the intended useful maximum length for distributed memories. Assuming you are using a Spartan 6 device, you can find information on what the useful supported distributed memory sizes are here: http://www.xilinx.com/support/documentation/user_guides/ug384.pdf page 52.

Upvotes: 1

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