CODEWITHSUNDEEP
veriloghdltest-bench
obtur
obtur

Reputation: 33

Can Verilog testbenches work with a real clock?

I wrote a counter in Verilog, and then a testbench to test it. My testbench gives the correct results, so my code is OK. But, it gives the result of a long time instantly.

Is it possible to take the result with real time? I mean in every one second, my testbench will produce a new line of results? If it is possible, how?

Upvotes: 1

Views: 1646

Answers (1)

toolic
toolic

Reputation: 62037

It is not exactly clear to me what you are trying to accomplish, but the $system system task can be used to execute a shell command during simulation. If you execute sleep 1 as follows, the simulation will pause for 1 second of wall-clock time for each time step. This will cause your simulation to display a message once per second. Of course, your simulation will be extremely slow. Note that $system is not part of the IEEE Standard for Verilog (but it is part of the System-Verilog Std).

`timescale 1ns/1ns

module tb;

initial begin
    $timeformat(-9, 1, "ns");
    #5 $finish;
end

integer sec = 0;
always begin
    #1;
    $system("sleep 1");
    sec = sec + 1;
    $display("seconds = %0d, time = %0t", sec, $time);
end

endmodule

This prints the following:

seconds = 1, time = 1.0ns
seconds = 2, time = 2.0ns
seconds = 3, time = 3.0ns
seconds = 4, time = 4.0ns
$finish called from file "tb.v", line 8.
$finish at simulation time                5.0ns

Upvotes: 3

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