CODEWITHSUNDEEP
vhdllava
Cactus
Cactus

Reputation: 27626

Assigning to output signal and changing register value from the same branch in an RTL block

In VHDL, I can write something like this to change the value stored in the register COUNTER and assign to an output signal from the same branch of a condition:

entity AssignTest is
  port (CLK: in std_logic; 
        OUTPUT: out std_logic_vector(1 downto 0));
end AssignTest;

architecture Behavioral of AssignTest is
  signal CLK: std_logic := '0';
  signal COUNTER: std_logic_vector (3 downto 0) := (others => '0');
begin
  process (CLK)
  begin
    if rising_edge(CLK) then
      OUTPUT <= "10";
      if COUNTER = "1001" then
        COUNTER <= "0000";
        OUTPUT <= "11";
      else       
        COUNTER <= std_logic_vector(unsigned(COUNTER) + 1);
      end if;
    end if;
  end process;
end Behavioral;

Is there a way to do something similar in Kansas Lava? You can, of course, do both individually with something like

runRTL $ do
  counter <- newReg (0 :: U4)
  CASE [ IF (reg counter .==. 9) $ counter := 0
       , OTHERWISE $ counter := reg counter + 1
       ]
  return $ mux (reg counter .==. 9) (2, 3)

However, I am looking for a way to not have to write out the reg counter .==. 9 condition twice, since in my real code, I'd be changing a ton of internal registers and assigning to a lot of output signals in many branches (and, ideally, I wouldn't even be assigning all outputs from all branches; rather, I'd have some default assignment).

Upvotes: 0

Views: 1457

Answers (0)

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