A73rnA
A73rnA

Reputation: 151

Signal assignment in VHDL process

I have a question regarding signal assignments in a process: How long is each signals life interval?

Say i have this process:

process(T)
begin
    if T(0) = '1' then
        x<='1';
    elsif T(1) = '1' then
        y<='0';
    end if;
end process ;

and T is incremented every cycle. Will the signal X remain '1' in the second run of the process?

Upvotes: 0

Views: 248

Answers (1)

Andreas Bombe
Andreas Bombe

Reputation: 2470

A signal keeps its value until it is assigned another one. Given that your code only ever assigns '1' to x and '0' to y, they will keep these values forever after the first time they are assigned.

Upvotes: 1

Related Questions