CODEWITHSUNDEEP
vhdl
Lotley
Lotley

Reputation: 3

Signal assignment method

I am new to VHDL and have had some difficulty in performing the assignment of two different values to the same signal inside a process. For example,

process(CLK)

 if rising_edge(CLK) then

   OUTPUT0 <= X(0);
   OUTPUT1 <= X(1);
   OUTPUT2 <= X(2);

   LED0 <= VALUE;

   OUTPUT0 <= Y(0);
   OUTPUT1 <= Y(1);
   OUTPUT2 <= Y(2);

   LED1 <= VALUE;

 end if;
end process;

Note that VALUE is an output dependent on the values assigned to OUTPUT0, OUTPUT1, OUTPUT2.

From what I understand in a process is that the last assignment to the same signal is always applied. What I am trying to do is apply two different sets of values to one set of inputs, map the output and it be done sequentially. I have tried separate processes tied to the same clock, a FSM to attempt to move sequentially and so on. At this point I have exhausted my knowledge of things to try.

My question is: What would be the best way to sequentially assign two values to one input and map its output in order?

EDIT:

As per Brian's suggestion on the state machine I had went ahead and implemented one again and found my error and fixed it. This gave the sequential assignment I was looking for.

I was reading 2 addresses from one instance of 32x1 distributed RAM which is the reason for a sequential assignment. Apologies for not providing the best example. Below is my final implementation:

RAM_READ_FSM : process(CLOCK) -- FSM to read the RAM addresses sequentially

    begin

        if rising_edge(CLOCK) then
        
            case curr_state is
            
             when S0 => if SW2 = '1' then
             
            RAMADDR0 <= XYVEC(5); -- Y addresses
            RAMADDR1 <= XYVEC(6);
            RAMADDR2 <= XYVEC(7);
            RAMADDR3 <= XYVEC(8);
            RAMADDR4 <= XYVEC(9);
            
            LED1 <= RAMOUT;
            
            curr_state <= S1;

         else
         
         curr_state <= S0;
         
            end if;
            
             when S1 => if SW2 = '1' then
                        
            RAMADDR0 <= XYVEC(0); -- X addresses
            RAMADDR1 <= XYVEC(1);
            RAMADDR2 <= XYVEC(2);
            RAMADDR3 <= XYVEC(3);
            RAMADDR4 <= XYVEC(4);
            
            LED2 <= RAMOUT;
            
            curr_state <= S0;
            
            else
            
            curr_state <= S1;
            
            end if;
        end case;
    end if;
end process;

Upvotes: 0

Views: 374

Answers (1)

user1818839
user1818839

Reputation:

  1. The signals should be driven from the same process : multiple drivers would interfere with each other..

  2. See Is process in VHDL reentrant? on signal assignment semantics.

  3. now you can see there is need for some delay (even just 2 delta cycles, if the logic calculating VALUE is just a simple signal assignment) between the X and LED0 assignments.

  4. You were on the right lines with a state machine but you didn't say anything about how it failed. Worth adding that to the Q to get a fuller answer.

  5. Meanwhile there is a simple way to add delay :

like

LEDS : process is
begin

   wait until rising_edge(CLK);
   OUTPUT0 <= X(0);
   OUTPUT1 <= X(1);
   OUTPUT2 <= X(2);
    
   wait until rising_edge(CLK);
   LED0 <= VALUE;
  
   wait until rising_edge(CLK);
   OUTPUT0 <= Y(0);
   -- etc
end process LEDS;

Upvotes: 1

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