Reputation: 11
Even after doing an extensive research in the web, I have not come across a clean explanation of how signal assignment happens in a vhdl testbench with wait statements.
Could somebody please elaborate how does it work?
For e.g. within the process I have something like this:
wait until spi_sck = '1';
wait until spi_sck = '0';
tb_rx_bytes(7) <= spi_mosi;
How can I make sure the tb_rx_byte
assignment happens?
More specifically, my problem is that the last tb_rx_bytes
does not get set to the spi_mosi
assignment.
for j in 31 downto 0 loop
wait until spi_sck = '1';
wait until spi_sck = '0';
tb_rx_bytes(j) <= spi_mosi;
end loop;
Upvotes: 1
Views: 1021
Reputation: 835
This is one of the things which confuses some people when they start working with VHDL, particularly those with a background in programming languages. In VHDL, signal assignments are not updated immediately like programming languages. Instead, the assignments are booked, and the signal values are updated when the process suspends. That happens when
So, in your case the value of tb_rx_bytes will be updated except bit 0, which is only booked for update in the last iteration of the loop. But the value is not updated, until one of the two conditions mentioned above are met.
Upvotes: 0
Reputation: 28965
In order to see the effect of your signal assignment 3 conditions must hold successively:
spi_sck
and the new value is '1'
spi_sck
and the new value is '0'
I guess it is the last condition that fails and prevents the last assignment from having visible effects. Add a wait for 1 ns;
after your end loop;
statement.
Upvotes: 1