sykatch
Reputation: 301
Signal vector assignment in VHDL
I have these signals in architecture:
signal sign1: STD_LOGIC_VECTOR (21 downto 0);
signal sign2: STD_LOGIC;
Then in some process I have this assignment. What does it mean? What value will be in sign2? 21th bit of the vector?
sign2 <= sign1(21);
Upvotes: 1
Views: 1932
Answers (1)
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