CODEWITHSUNDEEP
vhdl
cjgriscom
cjgriscom

Reputation: 176

Do VHDL signal assignments set destination value or reference?

I apologize for the cumbersome wording of the title question, but can't think of any other way to ask it concisely. I'm aware that this is quite different from, yet analogous to, the pass-by-value vs reference dichotomy. I am wondering which of the following snippets of code would behave identically:

Declarations:

Port (source : in STD_LOGIC);
...
signal destination : STD_LOGIC := '0';

#1 - Sets the "value" on clock

process (clk) begin 
    if falling_edge(clk) then
       if source = '1' then
            destination <= '1';
        else
            destination <= '0';
        end if;

#2 - Sets a "reference" universally

-- Top-Level
destination <= source;

#3 - Sets the (value? reference?) on clock

process (clk) begin 
    if falling_edge(clk) then
        destination <= source;

Snippet #1 will change the value of the destination to match the source every falling edge of the clock cycle. In #2, the destination will become 'connected' to the source, and changes in the source will be followed by the destination regardless of the clock cycle. I am unsure about #3; does it behave like #1 or #2, taking the value of the source and putting it in the destination, or linking the two together as in the top-level assignment?

Upvotes: 1

Views: 308

Answers (1)

Matthew
Matthew

Reputation: 13967

#1

This process has a sensitivity list. When there is an event (a change in value) on any signal in a sensitivity list, the process starts executing. This process has one signal in the sensitivity list - clk - so when there is a change on that signal, the process starts executing. If that change were a rising edge, then the condition in the if statement evaluates to FALSE and so no more lines of code are executed and the process suspends (goes to sleep). If that change were a falling edge, however, then the condition in the if statement evaluates to TRUE and so, depending on the value of source, one of two lines of code is executed that assigns a value to destination. Here's the really important bit:

When a line of code containing a signal assignment (<=) is executed in VHDL (and the effect is to change the value of the target signal - the signal on the LHS of the assignment), an event is placed on the what I shall call the event queue.

The event queue is the simulator's ToDo list and events placed on it will be actioned at some future time. If there is no explicit delay specified then that event with be actioned on the next simulation cycle (or delta cycle). Bear with...

So, assuming that the effect of executing the lines containing signal assignments is to change the value of destination, then the effect of executing those lines is to place an event on the event queue. The process then suspends.

Once all the processes have suspended, the simulator takes a look at its event queue and moves the simulation time forward to the time of the next event on the queue. In this case, that event will have been scheduled for the next simulation cycle, so the simulator time advances one simulation cycle and the events for that cycle are actioned. If any sensitivity list contains a signal that has been caused to change by actioning one of those events, then the whole cycle starts again: processes get executed, lines of code containing signal assignments get executed, new events get place on the event queue for some future time...

#3

From the point of view of this discussion, case #3 is exactly the same as case #1. A falling edge on clk will cause a line of code containing a signal assignment to be executed and, if a change of value on the target signal (destination) is required then an event will get placed on the event queue to action that change on the next simulation cycle.

#2

Case #2 clearly does not depend on clk, so is different. However, #2 is an example of a concurrent signal assignment. This is effectively and implicit process: you get an implicit sensitivity list, which contains any signal on the RHS of the signal assignment. In this case, the implicit sensitivity list contains one signal - source. So, if there is an event on source then the (implicit) process starts executing resulting in a line of code containing a signal assignment being executed and hence resulting in an event being placed on the event queue (which will be scheduled for the next simulation cycle).

So, to answer your question: "do VHDL signal assignments set destination value or reference?"

The value that is placed on the event queue (ie the value to which the target signal is to be driven) is the value that was evaluated at the time the line of code containing the signal assignment was executed.

So, in case #3, the value to assign to destination which is placed on the event queue is the value that source signal had at the time the line of code containing the signal assignment was executed. If you want to cal that 'pass by copy' then do so, but I wouldn't take that analogy very far.

Note: The LRM - the VHDL standard - uses the terminology Projected Output Waveform for what I call the event queue.

Upvotes: 3

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