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vectorvhdl
TheAlPaca02
TheAlPaca02

Reputation: 523

VHDL Vector passing

I want to pass a value from one vector to another. Can I simply do it this way?

vector_one : out STD_LOGIC_VECTOR (3 downto 0);
vector_two : out STD_LOGIC_VECTOR (3 downto 0);

vector_one <= vector_two;

Upvotes: 1

Views: 748

Answers (2)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The vector_one is an output port (mode out), and reading this is allowed in VHDL-2008, so you can do:

vector_one <= vector_two;

However, in VHDL-2002 it is not allowed to read an output port, so you must drive both outputz from the source, say vector_source, like:

vector_one <= vector_source;
vector_two <= vector_source;

Generally, it should be avoided to duplicate an output signal like that, since it is not obvious from the use of that module that some output are driven with identical values, which makes it harder to understand the module use.

Upvotes: 2

CJC
CJC

Reputation: 817

you can but you need to take note that if you will need to use vector_one in your module before it gets used outside meaning that the module will need to hold information about it. Then you will need to declare an internal signal in order to work on it.

example: 

entity exampleModule is 
port( iClk : in STD_LOGIC;
      iTrigger    : in STD_LOGIC;
      iVector_one : out STD_LOGIC_VECTOR (3 downto 0);
      oVector_two : out STD_LOGIC_VECTOR (3 downto 0));
end exampleModule ;

Architecture RTL of exampleModule is
    signal mVectorBuff : std_logic_vector (3 downto 0);
begin 
    process (iClk) begin
       if rising_edge (iClk) then
           if iTrigger then mVectorBuff <= iVector_one;
           end if;
       end if; 
    end process;

    oVector_two <= mVector_one;
end Architecture RTL;

Upvotes: 0

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