CODEWITHSUNDEEP
vhdl
user1814001
user1814001

Reputation: 1

Multiplication of a scalar with a vector

I am writing code in VHDL in which a number is multiplied by a vector. But it gives an error.

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multi is
 port (    clk   :  in std_logic;
          ipixel :  in std_logic_vector(15 downto 0);
          opixel  :  out std_logic_vector(15 downto 0)
      );

end entity multi;

architecture rtl of multi is
begin

process (clk) begin
  if rising_edge (clk) then

        opixel (15 downto 11) <=  std_logic_vector(unsigned(ipixel(15 downto 11))*3);
        opixel (10 downto 5)  <= std_logic_vector(unsigned(ipixel(10 downto 5))* 3);
        opixel (4 downto 0)   <= std_logic_vector(unsigned(ipixel(4 downto 0))* 3);

    end if;
end process;
end architecture rtl;

The error is:

Target slice 5 elements; Value is 10 elements

Upvotes: 0

Views: 2050

Answers (1)

baldyHDL
baldyHDL

Reputation: 1387

When you multiply an unsigned value with a natural, this is defined in NUMERIC_STD as follows:

function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
    return L * TO_UNSIGNED(R, L'LENGTH);
end "*";

Return value will result in 2 * length of your unsigned factor!

Upvotes: 3

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