CODEWITHSUNDEEP
vhdl
cc6g11
cc6g11

Reputation: 487

How to easily group and drive signals in VHDL testbench

Let's say I have 3 control signals A, B and C.

In the testbench is there a function in VHDL to group this and iterate all cases quickly (to enable them to be iterated with a for loop for example) rather than write out 8 cases.

Psuedo code example:

for i in range 0 to 7
 grouped_signals <=std_logic_vector(to_unsigned(i,3)

Upvotes: 2

Views: 930

Answers (1)

user1155120
user1155120

Reputation:

It can be a signal assignment where the target is an aggregate:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity agg_assign is
end entity;

architecture foo of agg_assign is
    signal A, B, C: std_logic;
begin
    process
    begin
        wait for 10 ns;
        for i in 0 to 7 loop
            (A, B, C) <= std_logic_vector(to_unsigned(i, 3));
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;

And that produces:

agg_assign.png

Upvotes: 3

Related Questions