CODEWITHSUNDEEP
verilogfsm
Shikhar Makkar
Shikhar Makkar

Reputation: 1

Verilog and ASM implementation

In the question below,

The ASM chart shows that value of q_next is compared to 0 to proceed to next state but before q_next is compared, the value of q is already updated with q_next, so if we compare the value of q with 0, will the results be same in terms of timing and other parameters?

Also what should be the types of q_next and q ? Should they be reg or wire?

I have attached the screenshots of the ASM chart and the Verilog code. I also don't understand the timing implications of conditional box (in general, can't we put the output of a conditional box in a separate state which doesn't depend on the output of the conditional box)?,

like when in the wait1 state, we check the value of sw and if true, we decrement the counter and then check if counter has reached to zero and then asser db_tick. I want to understand the time flow when we move from wait1 and increment counter and assert db_tick. Are there any clock cycles involved between these stages, that is moving from a state to a conditional box?

Also in the verilog code, we use q_load and q_tick to control the counter. Why these signals are used when we can simply control the counter in the states?

Is it done to make sure that the FSM (control path) controls the counter (data path)? Please explain. Thanks in advance.

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Upvotes: 0

Views: 2822

Answers (1)

wilcroft
wilcroft

Reputation: 1635

In the question below, the ASM chart shows that value of q_next is compared to 0 to proceed to next state but before q_next is compared, the value of q is already updated with q_next, so if we compare the value of q with 0, will the results be same in terms of timing and other parameters?

No. When q_next has a value of 0, q still contains a value of 1 until it's updated on the next positive clock edge. If you check for q==0, you will spend an extra clock cycle in each wait state.

Also what should be the types of q_next and q? Should they be reg or wire?

Either. reg types (like q_reg) mean they're assign a value in an always block, while wire types (like q_next) are assigned using the assign statement or as the output of a submodule.

I also don't understand the timing implications of conditional box (in general, can't we put the output of a conditional box in a separate state which doesn't depend on the output of the conditional box)?, like when in the wait1 state, we check the value of sw and if true, we decrement the counter and then check if counter has reached to zero and then asser db_tick. I want to understand the time flow when we move from wait1 and increment counter and assert db_tick.

Here's the flow of operations for a single clock cycle while in the wait1 state:

  • Is SW==1? If not, do nothing else, and go to state zero. Those operations will be done on the next cycle.
  • If SW==1, compute q_next, and assign that value to q for the next cycle.
  • Is q_next==0? If not, remain in wait1 for the next cycle and repeat.
  • Otherwise, assert db_tick=1 for this clock cycle, and go to state one.

If you split up the two conditionals into two separate states, counting down to 0 will take twice as long.

Are there any clock cycles involved between these stages, that is moving from a state to a conditional box?

Based on the diagram, all operations (comparing sw, subtracting from q, etc) within a given state - that is, one of the dotted-line boxes - are performed in a single clock cycle.

Also in the verilog code, we use q_load and q_tick to control the counter. Why these signals are used when we can simply control the counter in the states? Is it done to make sure that the FSM (control path) controls the counter (data path)?

You could do it that way too. Just be sure to assign a value to q_next in the default case to prevent latching. Splitting the data path and control path into separate always blocks/assign statements does improve readability though, IMO.

Upvotes: 0

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