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initializationverilogfsm
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Reputation: 3

FSM state machine in Verilog

If there is no reset in the input, how do you set the initial state to state_0 ? 

reg[2:0]    state;


localparam  s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 
3'b100, s5 = 3'b101;    
assign  state = s0; /* NOT SURE IF THIS IS RIGHT!*/


localparam  i=0, j=64, k=0, h=0; 


always @ ( posedge clk ) begin

case( state )

        s0: ........

Upvotes: 0

Views: 1700

Answers (1)

darsnack
darsnack

Reputation: 925

No that will not work, because an assign statement will force state = s0 all the time. The compiler will also complain about multiple drivers setting state. If there is no reset signal, one option is:

initial begin
  // set any initial values
  state = s0;
end

This would go in place of where you have the assign statement. This works well in simulation, but an even better practice would be to modify your state logic:

localparam  s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
reg [2:0] state, next_state;

always @(posedge clk) begin
  state <= next_state;
end

always @(state) begin
  case (state)
  // modify this state logic to reflect your FSM
  s0: next_state <= s1;
  s1: next_state <= s2;
  s2: next_state <= s3;
  s3: next_state <= s4;
  s4: next_state <= s5;
  s5: next_state <= s0;
  // this controls the behavior at bringup w/o a reset
  // you should include a default case even with a reset
  default: next_state <= s0;
  endcase
end

always @(state) begin
  case (state)
  // modify this output logic to reflect your FSM
  s0: // set your output signals accordingly
  s1: // set your output signals accordingly
  s2: // set your output signals accordingly
  s3: // set your output signals accordingly
  s4: // set your output signals accordingly
  s5: // set your output signals accordingly
  // this controls the behavior at bringup w/o a reset
  // you should include a default case even with a reset
  default: // set all outputs to 0
  endcase
end

The separation of the logic into the clocked always block and the combinational state transition logic above helps to create a latch-free design. I know it's more than what you asked, but this coding style helps create good synthesized designs.

Upvotes: 1

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