CODEWITHSUNDEEP
verilog
Yuerno
Yuerno

Reputation: 843

How does a state transition work with a Verilog FSM code-wise?

Verilog code that my question is about

In the code linked above, which is a standard Verilog FSM, I want to clear up exactly how the state transition works. The sequential portion of the code does the assigning for the next state, but my confusion is how does it go from that sequential section to selecting the proper next state from the combinational section of code?

Is it that at the clock edge, since the "current state" is being re-assigned a new value at the clock edge, it automatically triggers the sensitivity list in the combinational section of code, which is what then correctly selects the value of next state?

Upvotes: 0

Views: 172

Answers (1)

dave_59
dave_59

Reputation: 42788

In your example, @(*) is equivalent to @(state or start or restart). So any change to one of those signals causes next_state to get re-evaluated.

Upvotes: 1

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