CODEWITHSUNDEEP
macrosverilogsystem-verilogstringification
Zamfir Yonchev
Zamfir Yonchev

Reputation: 161

How to create a string from a pre-processor macro with arguments

I'm trying to stringify a macro in System Verilog, so I can use it in a string for printing.

I created a STRINGIFY macro:

`define STRINGIFY(x) `"x`"

as suggested here: How to create a string from a pre-processor macro

However, the macro I'm trying to stringify takes arguments.

Consider the following code:

`define STRINGIFY(x) `"x`"
`define HPATH(signal) top.chip.block.signal
string hpath = `STRINGIFY(`HPATH(wire));
$display(hpath);                       // Output: "`HPATH(wire)"

I want the output to be "top.chip.block.wire" instead.

Notice that the HPATH macro takes an argument wire.

This is the example code run here: http://www.edaplayground.com/x/CKB

EDIT: The problem is that the `STRINGIFY macro stops the expansion of the macro inside when the macro inside has arguments. For example:

`define STRINGIFY(x) `"x`"
`define HPATH top.chip.block
`define HPATH_SIGNAL(signal) top.chip.block.signal

$display(`"`HPATH`"); // correctly outputs "top.chip.block"
$display(`STRINGIFY(`HPATH)); // correctly outputs "top.chip.block"
$display(`"`HPATH_SIGNAL(sig)`"); // correctly outputs "top.chip.block.sig"
$display(`STRINGIFY(`HPATH_SIGNAL(sig))); // incorrectly outputs "`HPATH_SIGNAL(sig)"

It seems that the `HPATH_SIGNAL(sig) is not resolved when nested inside the `STRINGIFY macro

The question is why isn't the HPATH_SIGNAL(sig) expanded on the last line?

Here's the example code run: http://www.edaplayground.com/x/RF2

Upvotes: 1

Views: 3801

Answers (4)

kappajacko
kappajacko

Reputation: 11

I don't know when this was introduced to VCS, but you can force VCS to be LRM compliant using the below option.

-p1800_macro_expansion

This option is used for LRM compliance to support macro
expansion. This option produces results that are more LRM-
compliant and accurate especially for SystemVerilog macros.

Upvotes: 1

Zamfir Yonchev
Zamfir Yonchev

Reputation: 161

It seems to be a VCS issue.

When the same code is run on Icarus Verilog 0.10.0 and Riviera-PRO EDU 2015.06 simulators the output is correct.

The issue appears when running with VCS 2014.12 simulator.

Upvotes: 0

dave_59
dave_59

Reputation: 42616

I don't agree with the output you are getting on EDA playground. I am getting the desired output using ModelSim/Questa. Regardless of where the macro argument text is expanded before or after being passed through the outer level macro (The LRM says after) the `" should have allowed the macro that was passed through to be expanded.

Upvotes: 0

Emman
Emman

Reputation: 1234

An `" overrides the usual lexical meaning of " and indicates that the expansion shall include the quotation mark, substitution of actual arguments, and expansions of embedded macros. This allows string literals to be constructed from macro arguments.

A mixture of `" and " is allowed in the macro text, however the use of " always starts a string literal and must have a terminating ". Any characters embedded inside this string literal, including ", the " starts a string literal whose last charater is is terminated by the " of ".

`define HPATH(signal) `"top.chip.block.signal`"
`define W wire
module a;
  initial begin
    string hpath = `HPATH(wire);
    //string hpath = `HPATH(`W);
    $display("%s",hpath);
  end
endmodule

output : top.chip.block.wire

Hope you understand the context of `" and " (or just a macro definition)

Upvotes: 0

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