CODEWITHSUNDEEP
verilogiverilog
lkamp
lkamp

Reputation: 183

Connect 5-bit bus to 32-bit output bus

My design needs multiple multiplexers, all of them have two inputs and most are 32 bits wide. I started with designing the 32 bit, 2:1 multiplexer.

Now I need a 5 bit, 2:1 multiplexer and I want to reuse my 32 bit design. Connecting the inputs is easy (see code below), but I struggle to connect the output.

This is my code:

reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [4:0] result; // Output of the multiplexer.

multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, result);

When I run the code through iverilog, I get a warning that says that the multiplexer expects a 32 bit output, but the connected bus is only 5 bit wide. The simulation shows the expected results, but I want to get rid of the warning.

Is there a way to tell iverilog to ignore the 27 unused bits of the multiplexer output or do I have to connect a 32 bit wide bus to the output of the multiplexer?

Upvotes: 0

Views: 2520

Answers (2)

user5079076
user5079076

Reputation:

I think the problem relates to the output of the multiplexer which is still 5 bits wide. You can solve it by doing something like this:

reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [31:0] temp;
wire [4:0] result; // Output of the multiplexer.

multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, temp);
assign result = temp[4:0];

This can be easily tested in http://www.edaplayground.com/ using the code below: ( I have re-used @mcleod_ideafix's code)

// Code your testbench here
// or browse Examples

module mux #(parameter WIDTH=32) (
  input wire [WIDTH-1:0] a,
  input wire [WIDTH-1:0] b,
  input wire sel,
  output wire [WIDTH-1:0] o
);

  assign o = (sel==1'b0)? a : b;
endmodule

module tb;

  reg [31:0] a,b;
  wire [31:0] o;
  wire [4:0] r;

  reg sel;

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    a = 10; b = 20; sel = 1;
  end

  mux MM(a,b,sel,o);

  assign r = o[4:0];

endmodule

Let me know if you are still getting a warning.

Upvotes: 0

mcleod_ideafix
mcleod_ideafix

Reputation: 11428

I don't know of a #pragma or something like that (similar to #pragma argsused from C) that can be used in Verilog.

Xilinx ISE, for example, has a feature called "message filtering", which allows the designer to silence specific warning messages. You find them once, select them, choose to ignore, and subsequent synthesis won't trigger those warnings.

Maybe you can design your multiplexer in a way you don't need to "waste" connections (not actually wasted though, as the synthesizer will prune unused connections from the netlist). A more elegant solution would be to use a parametrized module, and instantiate it with the required width. Something like this:

module mux #(parameter WIDTH=32) (
  input wire [WIDTH-1:0] a,
  input wire [WIDTH-1:0] b,
  input wire sel,
  output wire [WIDTH-1:0] o
);

  assign o = (sel==1'b0)? a : b;
endmodule

This module has been tested with this simple test bench, which shows you how to instantiate a module with params:

module tb;
  reg [31:0] a1,b1;
  reg sel;
  wire [31:0] o1;

  reg [4:0] a2,b2;
  wire [4:0] o2;

  mux #(32) mux32 (a1,b1,sel,o1);
  mux #(5)  mux5  (a2,b2,sel,o2);

  // Best way to instantiate them:
  // mux #(.WIDTH(32)) mux32 (.a(a1),.b(b1),.sel(sel),o(o1));
  // mux #(.WIDTH(5))  mux5  (.a(a2),.b(b2),.sel(sel),.o(o2));

  initial begin
    $dumpfile ("dump.vcd");
    $dumpvars (1, tb);

    a1 = 32'h01234567;
    b1 = 32'h89ABCDEF;
    a2 = 5'b11111;
    b2 = 5'b00000;

    repeat (4) begin
      sel = 1'b0;
      #10;
      sel = 1'b1;
      #10;
    end
  end
endmodule

You can test it yourself using this Eda Playground link: http://www.edaplayground.com/x/Pkz

Upvotes: 4

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