CODEWITHSUNDEEP
inputiooutputverilogbus
Dhruv Patel
Dhruv Patel

Reputation: 496

Getting an error while using two bus wire as input and other two as output in verilog

I am trying to define my JD and JC Array of 4 wires where two is used as input and two as outputs. However, as shown in code, I am getting an error saying that declaration is illegal.

The error says:

ERROR:HDLCompilers:27 - "top.v" line 38 Illegal redeclaration of 'JC' ERROR:HDLCompilers:27 - "top.v" line 41 Illegal redeclaration of 'JD'

What is the best way to solve this?

Code sample

module top
(
    input wire mclk,             //50 MHz by default
    input wire rcclk,            //
    output  wire [7:0] seg,
    output wire dp,
    output wire [3:0] an,
    output wire [7:0] Led,
    input wire [7:0] sw,
    input wire [3:0] btn,

    //I/O pins
    input wire [3:0] JA,
    input wire [3:0] JB,
    //input wire [3:0] JC,

    input wire [3:2] JC,   //<< this is where I get the error
    output wire [1:0] JC,  //<< this is where I get the error

    input wire [3:2] JD,   //<< this is where I get the error
    output wire [1:0] JD   //<< this is where I get the error

);

Upvotes: 0

Views: 112

Answers (1)

Qiu
Qiu

Reputation: 5751

You can always define JC and JD as bidirectional pins (inout):

inout [1:0] JC,
inout [1:0] JD

Upvotes: 2

Related Questions