Unable to connect data wire between two submodules in verilog

Question

I have been trying for days and it is getting frustrated, I can't catch my mistake. I would appreciate if you someone would help me out. Following is my code where i have two modules inside a top module, after connecting everything perfectly the modules connection somehow won't work. The output from one submodule to input of another submodule is missing(if i remove my always code from first submodule). I can't even see the vc_buffers module in RTL schematic if the always code is uncommented inside my vc_buffers module.

Here is the complete code:

    `timescale 1ns / 1ps 
`include "parameters.v"

module router(
    clk,
    rst,
    flit_in,
    flit_out
    );

localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;

input clk, rst;

input [flit_size-1:0] flit_in;
wire [flit_size-1:0] flit_in;

output [flit_size-1:0] flit_out;
wire [flit_size-1:0] flit_out;

wire [flit_size-1:0] flit_buffers_fifo;
wire vc_empty_sig, vc_wr_en_sig;


//////////////////////////////////////////////////////////////////////////////////
////////////////////////////  VC BUFFER INST /////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////

vc_buffers vc_buffers_0(
    .clk(clk),
    .rst(rst),
    .vc_flit_in_0(flit_in),
    .vc_flit_out_0(flit_buffers_fifo),
    .vc_empty_0(vc_empty_sig),
    .vc_wr_en_0(vc_wr_en_sig)
    );


//////////////////////////////////////////////////////////////////////////////////
////////////////////////////  FIFO INST //////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////

fifo fifo_0(
     .clk(clk),
     .rst(rst),
      .wr_en(vc_wr_en_sig),
      .rd_en(),
     .flit_in(flit_buffers_fifo),
     .flit_out(flit_out),
     .empty(vc_empty_sig),
     .full()
    );


endmodule




//////////////////////////////////////////////////////////////////////////////////
////////////////////////////  VC BUFFER  /////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module vc_buffers(
    clk,
    rst,
    vc_empty_0,
    vc_flit_in_0,
    vc_flit_out_0,
    vc_wr_en_0
    );

localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;

input clk;
input rst;

input vc_empty_0;
wire  vc_empty_0;

input [flit_size-1:0] vc_flit_in_0;
wire [flit_size-1:0] vc_flit_in_0;

output vc_wr_en_0;
reg vc_wr_en_0;

output [flit_size-1:0] vc_flit_out_0;
reg [flit_size-1:0] vc_flit_out_0;



always @(posedge clk)
begin

    if(rst) begin
        vc_wr_en_0 <= 0;
    end else begin

        if (vc_empty_0) begin
            vc_wr_en_0 <= 1;
            //vc_flit_out_tmp_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
            //vc_flit_out_wire_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
            vc_flit_out_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
            vc_wr_en_0 <= 0;
        end else begin
                vc_wr_en_0 <= 0;
                // Discard buffer as there is no space in vc input buffer
        end

    end

end

endmodule




//////////////////////////////////////////////////////////////////////////////////
////////////////////////////  FIFO  //////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
module fifo(
     clk,
     rst,
      wr_en,
      rd_en,
     flit_in,
     flit_out,
     empty,
     full
    );



localparam flit_size = flit_ctrl + flit_data;
localparam fifo_depth = buffer_depth - 1;
localparam fifo_counter = fifo_depth;


input clk;
input rst;
input wr_en;
input rd_en;
input [flit_size-1:0] flit_in;
output [flit_size-1:0] flit_out;
output full, empty;

wire rd_en;
wire wr_en;
wire [flit_size-1:0] flit_in;

reg [flit_size-1:0] flit_out;    
reg [fifo_depth-1:0] head;
reg [fifo_depth-1:0] tail;
reg empty;
reg full;

reg [flit_size-1:0] memory [0:7];    

always @(posedge clk)
begin
    if ( rst) begin
        empty <= 1;
        full <= 0;
        flit_out <= 0;
        head <= 0;
        tail <= 0;
    end else begin

        case ( {wr_en, rd_en} )
        2'b10,
        2'b1x,
        2'b1z:
        begin
            if (empty) begin
                memory[head] <= flit_in;
                head <= (head == fifo_counter)?0:head+1;
            end else begin
                // do nothing
            end
        end
        2'b01,
        2'bx1,
        2'bz1:
        begin
            flit_out <= memory[tail];
            tail <= (tail == fifo_counter)?0:tail+1;
        end
        default:;
        endcase

    end


    if (head == fifo_counter) begin
        full <= 1;
        empty <= 0;
        end else begin
        end

    if (tail == fifo_counter) begin
        empty <= 1;
        full <= 0;
        end else begin
        end

end

endmodule

Answer 1

I have been trying to trace the actual root of problem. Apart from connecting the rd_en signal to top module, the real problem was assigning the 1s and 0s to the same rd_en and wr_en signals. After sorting it out everything looks cool. Atleast what I think, I would appreciate if someone can confirm that.

Old code:

if (vc_empty_0) begin
            vc_wr_en_0 <= 1;
            vc_flit_out_0 <= vc_flit_in_0; //Assign flit on input pins of router port 0
            vc_wr_en_0 <= 0;

I just removed the vc_wr_en_0 <= 0;

Thanks guys

Answer 2

That's because rd_en is unconnected in top module. Due to your case statement in fifo, output values such as flit_out won't change. So the input value "flit_buffers_fifo" of vc_buffer is constant and will be trimmed. if you initialize rd_en to 1'b1 you will see the changes. The better way is to put rd_en in list of top module signals and connect it to fifo module.