CODEWITHSUNDEEP
verilogyosys
Ghosty Toasty
Ghosty Toasty

Reputation: 19

Why do I get "Module port is neither input nor output" for all wires?

The error I get when trying to run the program is:

Yosys failed with code 1 unnamed.sv:5: ERROR: Module port `\D0' is neither input nor output.

This happens for all the wires.

module twobitmulti (A1, A0, B1,B0, P0, P1, P2, P3, C1, D0, D1, D2);

    input A1, A0;
    input B1, B0;
    output P0, P1, P2, P3;
    wire D0,D1,D2, C1;
    assign D0 =A1&&B0;
    assign D1 =A0&&B1;
    assign D2 =A1&&B1;
    assign C1 =D0&&D1;
    assign P0 =A0&&B0;
    assign P1 =D0^^D1;
    assign P2 =C1^^D1;
    assign P3 =C1^^D2;

endmodule

Upvotes: 1

Views: 287

Answers (1)

toolic
toolic

Reputation: 62073

The error tells you that D0 is in the port list in this line:

module twobitmulti (A1, A0, B1,B0, P0, P1, P2, P3, C1, D0, D1, D2);

but, you did not later declare D0 using the input or output keyword. A simple fix is to remove all the undeclared signals:

module twobitmulti (A1, A0, B1,B0, P0, P1, P2, P3);

The recommended coding style is to use ANSI ports:

module twobitmulti (
    input A1, A0,
    input B1, B0,
    output P0, P1, P2, P3
);

    wire D0, D1, D2, C1;
    assign D0 =A1&&B0;
    assign D1 =A0&&B1;
    assign D2 =A1&&B1;
    assign C1 =D0&&D1;
    assign P0 =A0&&B0;
    assign P1 =D0^^D1;
    assign P2 =C1^^D1;
    assign P3 =C1^^D2;
endmodule

Upvotes: 3

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