CODEWITHSUNDEEP
debuggingmodulesimulationverilog
node ninja
node ninja

Reputation: 32986

Verilog code compiles but why won't the simulation run?

My code consists of two files. One file has all the modules and one file has the test bench. When I try to run a simulation on the test bench, I get an unresolved reference error on this line in one of my modules:

Add_half (p[3], g[3], in_a[3], in_b[3]);

This line occurs in the module that my test bench calls.

What could be the problem?

This is the code for the test bench. `timescale 1ns/100ps

module CARRYLOOKAHEAD_TB;

reg [3:0] in_a_tb;
reg [3:0] in_b_tb;
reg in_c0_tb;
wire [3:0] s_tb;
wire c4_tb;

CarryLookAheadAdder DUT (.in_a(in_a_tb), .in_b(in_b_tb), .in_c0(in_c0_tb), .out_s(s_tb), .out_c4(c4_tb));
initial
begin
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b0000;
in_a_tb = 4'b0001;
in_c0_tb = 1'b1;
#50 
in_a_tb = 4'b0001;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b1111;
in_a_tb = 4'b0001;
in_c0_tb = 1'b0;
#50 
in_a_tb = 4'b1111;
in_a_tb = 4'b0000;
in_c0_tb = 1'b1;
#50 $stop;
#20 $finish;
end 
endmodule

This is the code for the module

module Add_half (sum, c_out, a, b);
input a, b;
output c_out, sum;
assign sum = a ^ b; 
assign c_out = a & b; 
endmodule

This is what gets called by the test bench

module CarryLookAheadAdder (in_a, in_b, in_c0, out_s, out_c4);
input [3:0] in_a;
input [3:0] in_b;
input in_c0;
output reg [3:0] out_s; 
output reg out_c4;
reg [3:0] p;
reg [3:0] g;
reg [3:0] c;
always@(in_a, in_b, in_c0)
begin
out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0;
Add_half (p[3], g[3], in_a[3], in_b[3]);
Add_half (p[2], g[2], in_a[2], in_b[2]);
Add_half (p[1], g[1], in_a[1], in_b[1]);
Add_half (p[0], g[0], in_a[0], in_b[0]);
out_c4 = c[4];
out_s[3] = p[3] ^ c[3];
out_s[2] = p[2] ^ c[2];
out_s[1] = p[1] ^ c[1];
out_s[0] = p[0] ^ c[0];
end  
endmodule

Upvotes: 1

Views: 8838

Answers (3)

jwmacdon
jwmacdon

Reputation: 86

In addition to Adam12 & GuanoLoco, just some general notes:

You are assign out_s[0] twice your CarryLookAheadAdder module

out_s[0] = (in_a[0] ^ in_b[0]) ^ in_c0;
...
out_s[0] = p[0] ^ c[0];

You aren't using your "g" variable output anywhere. You probably want this to be your "c", as I'm guessing this is your carry.

Upvotes: 2

GuanoLoco
GuanoLoco

Reputation: 81

In addition to the steps mentioned in Adam12's answer (add instance names, move out of always block), you need to change the type on your connection wires. 

reg [3:0] p;
reg [3:0] g;

should be 

wire [3:0] p;
wire [3:0] g;

This is because these are connected directly to the ports on the module. You would only use reg for something that was assigned in the always block.

Upvotes: 1

user597225
user597225

Reputation:

You're missing an instance name. Your simulator probably thinks that statement is a UDP instance so it gives an unresolved reference error during design elaboration. Compilation does not resolve module/UDP instances with definitions so these errors won't cause the compile to fail.

Try

Add_half add_half_inst(p[3], g[3], in_a[3], in_b[3]);

EDIT: Add_half is not a function or a task and can't be placed in an always block. It is a module and thus is instanced, not called. Remember you're modeling a logic circuit here.

Add_half add_half_0(p[3], g[3], in_a[3], in_b[3]);
Add_half add_half_1(p[3], g[3], in_a[3], in_b[3]);
...

Notice each instance has a unique name. You're instancing the same circuit 4 times and simply wiring the inputs and outputs. The instance name is required so they can be uniquely resolved using hierarchical identifiers.

This won't work as c is [3:0]

out_c4 = c[4];

Someone might mention a loop but I think you should ignore those for now even though they are appropriate here.

Upvotes: 3

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