Verilog GCD execution errors

Question

Re:Edit

I was able to solve that issue and move on to simulate the waveform using the testbench I had written, unfortunately there is no waveform from my main function getting generated.

My Testbench:

`timescale 1ns/1ps
module gcd_test();

reg [15:0] a,b;
reg clk, rst;

gcd uut(a,b,clk,rst);

initial begin

rst = 1;
a = 16'b0000000000001100;
b = 16'b0000000000000011;

end

initial begin
rst = 0;
end

always begin
#50
clk = 0;
#50
clk = 1;
end


endmodule

My output waveform is a couple of zzzz (as if my code was bored of execution). I check the output from the testbench, its good but the same isnt true for my main function. The output wave isnt as it should be. Again am I wrong with my testbench or parsing of the value from my testbench to the main?

TIA.

+++++++++++++++++++++++++++++++++++++++++++++

I am trying to execute a GCD function using Verilog HDL and I am utilizing a simple algorithm to execute this operation. However I keep stumbling across a number of errors during my execution.

My code:

module gcd(
input [15:0] a,
input [15:0] b,
input clk,
input rst);

reg [15:0] ra;
reg [15:0] rb;
reg [15:0] gcd;
reg done;
reg [2:0] state;
parameter start = 2'h1;
parameter check = 2'h2;
parameter comp = 2'h3;
parameter lastend = 2'h4;


always @ (posedge clk or posedge rst)
if (rst)
begin
    ra <= 16'h0;
    ra <= 16'h0;
    gcd <= 16'h0;
    state <= start;
end

else begin
    case(state)
        start: //status 0
                begin
                    ra <= a;
                    rb <= b;
                    state <= check;
                end
        check:  //Status 1
                begin
                    if ((ra == 16'h0) || (ra == 16'h0))
                    begin
                        state <= lastend;
                    end
                    else begin
                        state <= comp;
                    end
                end
        comp: //status 2
                begin
                    if(ra > rb) //Compare ra and rb
                    begin
                        ra = ra - rb;
                        if((ra < 16'h0) || (rb < 16'h0)) //Compare ra and rb and if either has become 0
                        begin
                            done = 1'h0;
                            state <= lastend;
                        end
                        else begin
                            state <= comp;
                            gcd <= ra;
                        end
                    end
                    else if (rb > ra) //Compare ra and rb
                    begin
                        rb = rb - ra;
                        if((ra < 16'h0) || (rb < 16'h0))//Compare ra and rb and if either has become 0
                        begin
                            done <= 1'h0;
                            state <= lastend;
                        end
                        else begin
                            state <= comp;
                            gcd <= ra;
                        end
                    end
                    else if(ra == rb) //Finally gcd found ra == rb
                        begin
                            gcd <= ra;
                            done <= 1'h0;
                            state <= start;
                        end
        lastend: //status 3
                        begin
                            gcd <= 16'h0;
                            done <= 1'h0;
                        end

    endcase
end
endmodule                       

Error (10170): Verilog HDL syntax error at gcd.v(85) near text "endcase"; expecting "end"

Or

Error (10163): Verilog HDL error at gcd.v(53): illegal name "lastend" used in expression
Error (10163): Verilog HDL error at gcd.v(66): illegal name "lastend" used in expression

with an extra end appended to the code.

Also, I have backtracked the code and seemed to have found all begins with appropriate ends.

Any suggestion is very helpful.

Answer 1

This begin:

        comp: //status 2
                begin

does not appear to have a matching end.