CODEWITHSUNDEEP
verilogsystem-verilog
Karan Shah
Karan Shah

Reputation: 1992

Wait for A Bit Change in Same Timestep in SV

Here is the code

module m;
  bit x;

  initial
  begin
    fork
      begin
        wait(x == 1);
        wait(x == 0);
      end
      begin
        @(x == 1);
        @(x == 0);
      end
      #10 $display("Timeout");
    join_any
    disable fork;
  end

  initial
  begin
    #5;
    x = 1;
    // Some other Logical Stuff
    x = 0;;
  end     
endmodule

Now in this code, Timeout will happen, because x = 1 & x = 0 is done in the single time step.

One solution is to provide delay between x = 1 & x = 0, then both waits will work fine.

Is there any other method, which can work without providing hard-coded delays?

Note :- With events or semaphores like stuff, this problem can be solved. But I am looking for the answer in terms of coding style or methods, which can work without usage of events.

Upvotes: 1

Views: 822

Answers (1)

H.Modh
H.Modh

Reputation: 448

There are several ways, which you can use here like event, semaphore, flag, etc. I have added an event in your code. Please find a modified code in below link.
http://www.edaplayground.com/x/Ws3

There are other ways also like,
1. Assign value "1" to x, during its declaration
E.g., bit x=1;
2. Use blocking and nonblocking assignment together in your 2nd initial block.
E.g., 

initial  
  begin  
    #5;  
    x = 1;  
    // Some other Logical Stuff  
    x <= 0; // Add non-blocking assignment  
  end   
end

=> The second option is not a good coding practice, but it'll solve your issue as both the assignment statments will work on different regions.

Upvotes: 2

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