CODEWITHSUNDEEP
bit-manipulationveriloglogical-operators
ninesalt
ninesalt

Reputation: 4354

What is the difference between a logical and/or and a bit-wise and/or?

Assume a= 4'b1110, b= 4'b0010

What is the difference between A && B and A & B and what is the difference between A ||B and A | B? What is the result of each of them and how is it done?

I tried reading some of the questions/answers on SO but I couldn't find any definitive answers.

Upvotes: 1

Views: 3940

Answers (2)

toolic
toolic

Reputation: 62236

It is done by creating a Verilog testbench and running a simulation:

module tb;

reg [3:0] a, b;
initial begin
    a= 4'b1110;
    b= 4'b0010;
    $display("a&b  = 'b%b", a&b);
    $display("a&&b = 'b%b", a&&b);
    $display("a|b  = 'b%b", a|b);
    $display("a||b = 'b%b", a||b);
    #5 $finish;
end

endmodule

Output:

a&b  = 'b0010
a&&b = 'b1
a|b  = 'b1110
a||b = 'b1

Refer to the IEEE Std 1800-2012 for more details about Verilog operators.

Upvotes: 1

Marc B
Marc B

Reputation: 360872

logical deals purely with the true/false values. The component bits are irrelevant, there's just all-zeroes (false), and not-all-zeroes (true).

bitwise does exactly as the name suggests - it considers individual bits.

a = 42    00101010
b = 23    00010111
c = 0     00000000

a || b -> true       a && b -> true
a | b  -> 63         a & b  -> 2
a || c -> true       a && c -> false
a | c  -> 42         a & c  -> 0

In more detail:

a || b ->    00101010
          || 00010111
          -----------
             00111111 -> 63, which is non-zero, therefore -> TRUE

a | b is exactly the same, but since it's only dealing with the bits, the calculation stops at 63.

a && b ->    00101010
          && 00010111
          -----------
             00000010 -> 2 -> non-zero, therefore -> TRUE

If we add in d = 21:

a && d -> 42 && 21 ->      00101010
                        && 00010101
                        -----------
                           00000000 -> all-zeroes, therefore false

Upvotes: 4

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