CODEWITHSUNDEEP
verilogoperator-keywordlogical-operators
kaps
kaps

Reputation: 31

Logical && versus bitwise & in Verilog

Consider the following assignment

A1 = (b[3:0] ==c[3:0] & d[3:0]==e[3:0]) ? 1'b1 : 1'b0 ;

A2 = (b[3:0] ==c[3:0] && d[3:0]==e[3:0]) ? 1'b1 : 1'b0 ;

Are the 2 assignments equivalent or they could be different depending on tools? Is it possible that (b[3:0] ==c[3:0]) evaluated as T/F is dependent on tool Whether it stores T as '1' or '0'.

Upvotes: 0

Views: 1600

Answers (1)

dave_59
dave_59

Reputation: 42673

The result of the equality, relational and logical operators are defined in sections 11.4.4-7 of the IEEE 1800-2017 LRM. There is no room for implementation differences. Truth is defined as 1'b1, and false is defined as 1'b0.

Note there are slight differences in precedence between the logical and bitwise operators, and it's easy to mix them up when you start dealing with multiple bit results, so use the bitwise operators only if your intent is to deal with multi-bit results.

Upvotes: 1

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