CODEWITHSUNDEEP
verilogalu
user2925924
user2925924

Reputation: 45

Implementing ALU

I'm trying to implement an ALU given specific function codes.

For some reason, the code below doesn't run and has errors according to the compiler.

Error (suppressible): alu.v(61): (vlog-2388) 'result' already declared in this scope (alu).
Error (suppressible): alu.v(67): (vlog-2388) 'operand0' already declared in this scope (alu).
Error (suppressible): alu.v(67): (vlog-2388) 'operand1' already declared in this scope (alu).
Error (suppressible):alu.v(68): (vlog-2388) 'control' already declared in this scope (alu).
Error: (vlog-13069) alu.v(71): near "<=": syntax error, unexpected <=.
Error: alu.v(71): (vlog-13205) Syntax error found in the scope following 'result'. Is there a missing '::'?

If I remove the declarations of result, operand0, operand1, and control as wire and regs I still get errors saying that "result" is out of scope or inaccessible. I'm really confused with this part and any help would be greatly appreciated.

I feel the problem is somewhere with regs and wires but I'm not sure.

module alu 
(
//--------------------------
// Input Ports
//--------------------------
input   [31:0]  operand0, 
input   [31:0]  operand1, 
input   [3:0]   control,
//--------------------------
// Output Ports
//--------------------------
output  [31:0]  result,
output          zero,
output          overflow
);



// Signal Declarations: local params




// Signal Declarations: reg





// Signal Declarations: wire


always @(*)
begin
case(control) 
4'b0000: result= operand0 | operand1; // OR 

4'b0001: begin
        result= operand0 & operand1; // AND
     end  
default: result = 4'b0;
endcase
end


endmodule

I changed the code above to the modified version. I still get errors though:

Now it says: (vlog-2110) Illegal reference to net "result". 3 times

Upvotes: 0

Views: 2466

Answers (1)

ssgr
ssgr

Reputation: 389

There are few issues with your code. There two ways of declaring inputs and outputs: 

  module alu (
         input   [31:0]  operand0, 
         input   [31:0]  operand1, 
         input   [3:0]   control,

         output reg [31:0]  result,
         output          zero,
         output          overflow
             );

and second method is :

   module (operand0,operand1,control,result,zero,overflow);
   input [31:0]  operand0; 
   input   [31:0]  operand1;
   input   [3:0]   control;
   output reg [31:0]  result;
   output          zero;
   output          overflow;

I hope you can see the difference. Hence, in your code you are re-declaring the inputs and outputs.

Also non-blocking assignments i.e. <= are usually used for sequential logic. For combinational logic blocking assignment is preferred i.e. =.

And if you want to define your output as reg, it has to be used inside always block otherwise define it as wire.

Your code can written as follows: 

module alu 
(
input   [31:0]  operand0, 
input   [31:0]  operand1, 
input   [3:0]   control,

output reg [31:0]  result,
output          zero,
output          overflow
);


always @(*)
begin
 case(control) 
  4'b0000: result= operand0 | operand1; // OR 

  4'b0001: begin
           result= operand0 & operand1; // AND
           end  
 default : result =4'b0;
endcase
end
 endmodule

Upvotes: 2

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