CODEWITHSUNDEEP
verilog
novice
novice

Reputation: 11

Verilog error when making alu : is not a constant

I am making an ALU, and I get an error. Why does it happen? The error message is:

sel is not a constant

module ALU(A,B,sel,aluout);
    input [3:0] A, B;
    input sel;
    output [7:0] aluout;
    wire c1;
    
    if(sel==0)
        begin
        fourbit_adder(A,B,Ci(1'b0),aluout,Co(c1));
        end
    else 
        begin 
        mult4(A,B,aluout);
        end

endmodule

module TB_multiplier(
);
    
    reg [3:0] m;
    reg [3:0] q;
    reg Sel;
    wire [7:0] p;
    
    ALU mult4_module(.p(p), .m(m), .q(q), .Sel(Sel));
    
    initial begin
    m = 4'b0000; q = 4'b0000; Sel = 1'b0;
    
    #5 m = 6; q = 7; Sel = 0;
    #5 m = 6; q = 7; Sel = 1;
    #5 m = 3; q = 5; Sel = 0;
    #5 m = 3; q = 5; Sel = 1;
    
    end

endmodule

Upvotes: 1

Views: 255

Answers (1)

Matthew
Matthew

Reputation: 13937

fourbit_adder is a block of hardware. mult4 is another block of hardware. Your code is asking for fourbit_adder to be present when sel is 0 and mult4 to be present when sel is 1. That breaks the laws of physics. Hardware cannot magically appear and disappear.

You need to instantiate both blocks unconditionally:

fourbit_adder(A,B,Ci(1'b0),aluout_fourbit_adder,Co(c1));
mult4(A,B,aluout_mult4);

and then drive your aluout output using a multiplexor, whose output is selected by your sel input, eg something like:

assign aluout = sel ? aluout_mult4 : aluout_fourbit_adder;

(I have not tested this. This is just to give you a general impression.)

Upvotes: 1

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