CODEWITHSUNDEEP
verilog
Coroner_Rex
Coroner_Rex

Reputation: 323

Verilog - Do I need to add delay with two always situation and also do always(*) sensitive to same input?

1) If I have two always block like:

input [3:0] m1;
reg [3:0] m1_r;

always @(posedge clk) begin
    m1_r = m1_r >> 2; //or #5 m1_r = m1_r >> 2;
end

always @(posedge clk) begin
    m1_r <= m1;
end

Do I need to delay for a small time to make sure that the m1's value has already load into m1_r?

2) If I use always @(*) block. Will this block be executed twice if I have the same input for two times? Or it just sensitive to different values?

Thanks!

Upvotes: 1

Views: 1827

Answers (1)

sharvil111
sharvil111

Reputation: 4381

Firstly, never make assignments to single variable in two different always blocks. This may result in race-around conditions and cause adverse effects in synthesis.

Referring to the trial code, you can not use always@* here due to some common reasons. This is a combinational circuit, for which the output should change whenever the RHS variables changes.

Verilog Event Regions

Here, when m1 changes, this block assigns the value to m1_r in NBA region (due to non-blocking assignment). Again, since m1_r changes in NBA region, the block executes second time; going into active region. This goes on forever on a single time stamp (Refer to the feedback path in image). Hence, either remove the non-blocking assignment or avoid using always @*. The code I am referring to is as below.

  always @(*) begin
    m1_r <= m1;
    m1_r = m1_r >> 2; //or #5 m1_r = m1_r >> 2;
  end

On the other hand, using always @(posedge clk) includes only clk in the sensitivity list. This will infer to a flip-flop. The block will execute only once at the edge of clock. But, here also, use of non-blocking assignments and single always block is recommended.

Upvotes: 3

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