CODEWITHSUNDEEP
vhdlfpga
MiJo
MiJo

Reputation: 569

In VHDL is there a difference between declaring one large vector and using slices of it verses declaring multiple small vectors?

--Example 1:
    signal x : STD_LOGIC_VECTOR(15 downto 0);
    --do something with x(15 downto 8);
    --do soemthing else with x(7 downto 0);

--Example 2:
    signal x0 : STD_LOGIC_VECTOR(7 downto 0);
    signal x1 : STD_LOGIC_VECTOR(7 downto 0);
    --do something with x0(7 downto 0);
    --do something else with x1(7 downto 0);

Is there any difference in the above with regards to how it would be implemented inside the FPGA, gate/LUT usage, performance, etc. And what about when an alias is used like.

--Example 3:
    signal x : STD_LOGIC_VECTOR(15 downto 0);
    alias x0 is x(15 downto 8);
    alias x1 is x(7 downto 0);
    --do something with x0(7 downto 0);
    --do something else with x1(7 downto 0);

I am new to this so couldn't figure out how to verify it myself, because in Xilinx ISE even if I regenerate the bit file on the same exact source code twice, the check-sum of the resulting bit file always changes. I guess it adds a time-stamp or some random number to the bit file?

Upvotes: 1

Views: 132

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The VHDL language does not specify how a design is to be implemented in a device, e.g. FPGA, so a synthesis tool can use whatever resources it wants, as long as the resulting implementation is equivalent with the VHDL source.

Tool vendors, e.g. Xilinx or Altera, does usually not specify the implementation method, but the tools are usually very good at optimizing the design, thus resulting in the smallest possible implementation.

The result is that equivalent VHDL designs will usually result in the same optimal implementation, in special if the design is simple so the synthesis algorithm can build complete internal design structures. Based on these reservations, the short answer is:

All 3 designs are assumed to be equivalent, so they will have the same implementation.

The consequence of this is that you can usually prioritize a design structure that is easy to write, read, review, and test, so you minimize the number of bugs and time spend, and then let the synthesis tool handle the implementation.

Finally, the art is then to understand when usually does not apply, and you therefore have write the design to fit the tool and device in order to get maximum performance and fill.

Upvotes: 3

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