CODEWITHSUNDEEP
vhdl
icecity96
icecity96

Reputation: 1227

VHDL illegal use of a signal declaraction

The following is my code:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS BEGIN 

PROCESS(CS, RD,WR) 
SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA<=T;
    ELSE IF WR='0' AND RD='1' THEN T<=DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

When I compile it, my compiler complains: 

Error: found illegal use of signal declaration in process declarative part

I know I'm using the wrong signal, but do not know where it's wrong.

Is there anyone can help?

Upvotes: 1

Views: 771

Answers (1)

user1155120
user1155120

Reputation:

Allowed process declarative items in a process declarative part are defined in IEEE Std 1076-2008 11.3 Process statement para 2:

 process_declarative_item ::=
        subprogram_declaration
      | subprogram_body
      | type_declaration
      | subtype_declaration
      | constant_declaration
      | variable_declaration
      | file_declaration
      | alias_declaration
      | attribute_declaration
      | attribute_specification
      | use_clause
      | group_type_declaration
      | group_declaration

You could note signal declaration isn't listed.

That signal declaration can be made in the architecture declarative part (before the begin most immediately following the reserved word architecture in the architecture body).

Making that change:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS 
    SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 

PROCESS(CS, RD,WR) 
--SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA<=T;
    ELSE IF WR='0' AND RD='1' THEN T<=DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

And your code analyzes.

(And whether it does what you intended isn't part of this question).

You can also use a variable in place of a signal:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY work4 IS
PORT (  CS: IN STD_LOGIC;
        RD: IN STD_LOGIC;
        WR: IN STD_LOGIC;
        DATA : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
 END work4; 
ARCHITECTURE behav OF work4 IS 
--    SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 

PROCESS(CS, RD,WR) 
--SIGNAL T: STD_LOGIC_VECTOR(3 DOWNTO 0);
    variable T: std_logic_vector (3 downto 0);
BEGIN 
 IF CS'EVENT AND CS = '1' THEN 
    IF WR='1' AND RD='0' THEN DATA <= T;
    ELSE IF WR='0' AND RD='1' THEN T := DATA;
    END IF;
END IF;
END IF; 
 END PROCESS; 
 END behav;

The use of a variable has several limitations. You can't use it outside the process and you can't see it in waveform displays.

Upvotes: 3

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