CODEWITHSUNDEEP
vhdl
Davide Pimpinella
Davide Pimpinella

Reputation: 11

Signal <signal> cannot be synthesized, bad synchronous description

I'm trying to implement a component that takes in input a base clock and as output a pattern accordingly to this scheme:

enter image description here

I'm getting this error, and i've tried to fix it in many ways following various suggestion also from stackoverflow, but nothing...

ERROR:Xst:827 - "E:/Progetti/nuovi/Clock_generator/CG_ex_3/clock_ex3.vhd" line 34: Signal check_0 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Some times the same error refer to pre_forma_clk

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clock_ex3 is
    Port ( base_clk : in  STD_LOGIC;
           forma_clk : out  STD_LOGIC);
end clock_ex3;

architecture Behavioral of clock_ex3 is
    signal pre_forma_clk : std_logic := '0';
begin

forma_clk <= pre_forma_clk;

pattern_generator : process(base_clk)  --line 34

    variable check_0 : natural := 0;
    variable check_1 : natural := 0;
    variable check_2 : natural := 0;
    variable check_3 : natural := 0;

begin
    if (rising_edge(base_clk)) then
        check_0 := check_0 + 1;
        if (check_0 = 15) then
            pre_forma_clk <= not pre_forma_clk;
        end if;
    end if;

    if (falling_edge(base_clk) and check_0 >= 15) then
        check_1 := check_1 + 1;
        if (check_1 = 10) then
            pre_forma_clk <= not pre_forma_clk;
        end if;
    end if;

    if (falling_edge(base_clk) and check_1 >= 10) then
        check_2 := check_2 + 1;
        if (check_2 = 15) then
            pre_forma_clk <= not pre_forma_clk;
        end if;
    end if;

    if (rising_edge(base_clk) and check_2 >= 15) then
        check_3 := check_3 + 1;
        if (check_3 = 10) then
            pre_forma_clk <= not pre_forma_clk;
            check_0 := 0;
            check_1 := 0;
            check_2 := 0;
            check_3 := 0;
        end if;
    end if;

end process;

end Behavioral;

I've already tried to separate IF conditions in different IFs... thanks for help

Upvotes: 0

Views: 950

Answers (1)

scary_jeff
scary_jeff

Reputation: 4374

Your question is pretty well answered here. The difference between that question and yours, is that the specific error in your code is that you have multiple if (rising_edge(clk)) then structures inside one process; a synthesis-eligible process can only contain one edge detector of this type.

Looking at your functional requirement, I would implement this using two separate rising and falling edge counters, each with their own process, then write another process implementing a state machine that works with these counters to implement the required state transitions and counter resets.

Upvotes: 2

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