CODEWITHSUNDEEP
moduleverilog
PPGoodMan
PPGoodMan

Reputation: 351

verilog component value passing

I am just beginning to learn verilog. I wrote two programs for that purpose. Here is my first program:

 module test1(i,o);
 input i;
 output o;

 wire[0:63] i;
 wire[0:63] o;

 assign o = i * 2.0;
 endmodule

 module test1_tb();
 reg[0:63] inp;
 wire[0:63] outp;
 initial
 begin
 assign inp = 2.0;
 $monitor("input=%f, output=%f",inp,outp);
 end
 test1 t1(inp,outp);
 endmodule

This gives me the following result when I run it in ModelSim:

 # input=2.000000, output=4.000000

Then I edited the above program as follows:

module test1(i1,i2,h1,w1,w2,b1);
input i1;
input i2;
input w1;
input w2;
input b1;
output h1;

wire[0:63] i1;
wire[0:63] i2;
wire[0:63] h1;
wire[0:63] w1;
wire[0:63] w2;
wire[0:63] b1;

assign h1 = 1/(1+ 2.718281828459**((-1.0)*(i1 * w1 + i2 * w2 + b1)));
endmodule

 module test1_tb();
 reg[0:63] i1;
 reg[0:63] i2;
 reg[0:63] w1;
 reg[0:63] w2;
 reg[0:63] b1;
 wire[0:63] h1;
 initial
 begin
 assign i1 = 0.05;
 assign i2 = 0.10;
 assign w1 = 0.15;
 assign w2 = 0.20;
 assign b1 = 0.35;
 $monitor("i1=%f, i2=%f, w1=%f, w2=%f, b1=%f, h1=%f",i1,i2,w1,w2,b1,h1);
 end
 test1 n1(i1,i2,h1,w1,w2,b1);
 endmodule

For this program I get the output:

 # i1=0.000000, i2=0.000000, w1=0.000000, w2=0.000000, b1=0.000000, h1=1.000000

It seems the module does not get the initial values in the second program. But all I did was adding few more input lines to the first program and changing the calculation.

Right now I don't know what's the error with this. Please help.

Upvotes: 0

Views: 204

Answers (1)

Unn
Unn

Reputation: 5108

The type reg is not designed to implicitly handle floating point math. As such, real constants assigned to the reg variables are rounded to the nearest integer (see IEEE1800-2012 Section 5.7.2, SystemVerilog LRM; sorry I dont have IEEE1364, Verilog LRM, to find the reference in there).

If you simply want to do some floating point math, you can use the real type which is the same as a double. Otherwise, if you want to do floating point math in hardware, youll need to deal with the complexities of it yourself (or borrow from an IP core). Also note that Verilog is not a scripting language, but a Hardware Descriptive Language, so unless you are trying to design hardware, you are much better off using Python, Ruby or Perl for general purpose stuff.

Upvotes: 2

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