Verilog HDL doesn't allow assignment of the value of one integer variable to another

Question

I am writing code for 16*4 RAM in Verilog. For each binary cell of memory, I am using an SR flip-flop. Initially, each cell is assigned 1'bx. I am using integers for loops as well as to store the value of the index of memory which is to be accessed using the variable k. Verilog doesn't allow me to assign k one of the values of the loop variable.

   module memory(addr, read_data, rw, write_data, clk);
// read_data is the data read
// rw specifies read or write operation. 1 for read and 0 for write
// write data is the data to be written
// addr is the address to be accessed   

task SRFlipFlop;
input d,r,s,clk; // d is the value initially stored
output q;  
begin
case({s,r})
{1'b0,1'b0}: q=d;
{1'b0,1'b1}: q=1'b0;
{1'b1,1'b0}: q=1'b1;
{1'b1,1'b1}: q=1'bx;
endcase
end
endtask

task decoder;     // a 4 to 16 line decoder
input [3:0] A;
input E;
output [15:0] D;
if (!E)
    D <= 16'b0000000000000000;
else
    begin
        case (A)
            4'b0000 : D <= 16'b0000000000000001;
            4'b0001 : D <= 16'b0000000000000010;
            4'b0010 : D <= 16'b0000000000000100;
            4'b0011 : D <= 16'b0000000000001000;
            4'b0100 : D <= 16'b0000000000010000;
            4'b0101 : D <= 16'b0000000000100000;
            4'b0110 : D <= 16'b0000000001000000;
            4'b0111 : D <= 16'b0000000010000000;
            4'b1000 : D <= 16'b0000000100000000;
            4'b1001 : D <= 16'b0000001000000000;
            4'b1010 : D <= 16'b0000010000000000;
            4'b1011 : D <= 16'b0000100000000000;
            4'b1100 : D <= 16'b0001000000000000;
            4'b1101 : D <= 16'b0010000000000000;
            4'b1110 : D <= 16'b0100000000000000;
            4'b1111 : D <= 16'b1000000000000000;
        endcase
    end
endtask

output reg [3:0] read_data;
input [3:0] write_data, addr;
input rw, clk;
reg [3:0] memory [15:0];
reg [3:0] r [15:0];
reg [3:0] s [15:0];
reg [3:0] select [15:0];
reg [15:0] out;
integer k;    // gives error
integer i,j;
initial 
  begin
    for (i = 0; i <= 15; i=i+1) 
        begin
            for (j = 0; j <= 3; j=j+1) 
                begin
                 memory[i][j] = 1'bx;
                 r[i][j] = 1'b0;
                 s[i][j] = 1'b0;
                 select[i][j] = 1'b0;
                end
        end
  end
  always @(rw or write_data or addr)  
  begin
     k = 16;
     decoder(addr, 1'b1, out);
     for (i = 0; i <= 15; i=i+1)
        begin
            if (out[i] == 1'b1)
                k = i;
        end
     for (i = 0; i <= 3; i=i+1)
        begin
            select[k][i] = 1'b1;
        end
     for (i = 0; i <= 3; i=i+1)
        begin
            s[k][i] = write_data[i] & !rw & select[k][i];
            r[k][i] = !write_data[i] & !rw & select[k][i];
        end 
  end
  always @(posedge clk)
  begin
   if (k == 16)
            begin
                for(i = 0; i <= 3; i=i+1) 
                    read_data[i] = 1'bx;
            end
        else
            for(i = 0; i <= 3; i=i+1) 
                begin
                  SRFlipFlop(memory[k][i],r[k][i],s[k][i],clk,memory[k][i]);
                  read_data[i] = memory[k][i];
                end
  end
endmodule

When I run it in Xilinx, I get the following output. How can I get rid of this error?

ERROR:Xst:528 - Multi-source in Unit <memory> on signal <_const0017> 

Answer 1

As @sharvil111 points out in their comment, you've got many illegalities.

• You can't instantiate modules inside an always block. Either use a generate block, or instantiate them individually.
• You can't have a sensitivity list with both edge-triggered and level-sensitive. If you want to generate registers/sequential logic, use always@(posedge clk) (with if statements as necessary). If you want combinational logic, use always@(*).
• Use non-blocking assignments (<=) inside an always @(posedge clk) block. Use of blocking assignments (=) can be dangerous.

There may be other errors as well, but these are most of the major ones.