my assert report statement written in the vhdl testbench is not showing in the console

Question

i am writing a code and test bench for 2 bit register, but in my test bench my assert report statement are not showing up in the console, when i run the simulation of the test bench. i am using Modelsim PE student version 10.4a and i am running the simulation for 100 ns. here is the test bench and console image plz help. thanks in advance.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;


entity reg_TB is            -- entity declaration
end reg_TB;

------------------------------------------------------------------

architecture TB of reg_TB is

    component reg
    port(   I:      in std_logic_vector(1 downto 0);
            clock:  in std_logic;
        load:   in std_logic;
        clear:  in std_logic;
        Q:      out std_logic_vector(1 downto 0)
    );
    end component;

    signal T_I:     std_logic_vector(1 downto 0);
    signal T_clock: std_logic;
    signal T_load:  std_logic;
    signal T_clear: std_logic;
    signal T_Q:     std_logic_vector(1 downto 0);

begin

    U_reg: reg port map (T_I, T_clock, T_load, T_clear, T_Q);

    -- concurrent process to offer the clock signal
    process
    begin
    T_clock <= '0';
    wait for 5 ns;
    T_clock <= '1';
    wait for 5 ns;
    end process;

    process                         

    variable err_cnt: integer :=0;

    begin                               

    T_I <= "10";
    T_load <= '0';
    T_clear <= '1';

    -- case 1
    wait for 20 ns;
    T_load <= '1';
    wait for 10 ns;
    assert (T_Q="10") report "Test1 Failed!" severity error;
    if (T_Q/=T_I) then
        err_cnt := err_cnt+1;
    end if;

    -- case 2               
    wait for 10 ns;
    T_load <= '0';
    wait for 10 ns;
    assert (T_Q="10") report "Test2 Failed!" severity error;
    if (T_Q/=T_I) then
        err_cnt := err_cnt+1;
    end if;     

    -- case 3
    wait for 10 ns;
    T_clear <= '0';                                        
    wait for 10 ns;
    assert (T_Q="00") report "Test3 Failed!" severity error;
    if (T_Q/=T_I) then
        err_cnt := err_cnt+1;
    end if;

    -- case 4
    wait for 10 ns;
    T_clear <= '1';
    wait for 10 ns;
    assert (T_Q="00") report "Test4 Failed!" severity error;
    if (T_Q/=T_I) then
        err_cnt := err_cnt+1;
    end if;

    -- summary of all the tests
    if (err_cnt=0) then 
        assert false
        report "Testbench of register completely successfully!"
        severity note;
    else
        assert true
        report "Something wrong, check again pls!"
        severity error;
    end if;

        wait;

    end process;

end TB;

------------------------------------------------------------------
configuration CFG_TB of reg_TB is
    for TB
    end for;
end CFG_TB;
------------------------------------------------------------------

Answer 1

If you sprinkle report statements for err_cnt immediately following the if statements in each test case:

    if (T_Q/=T_I) then
        err_cnt := err_cnt+1;
    end if;
    report "err_cont = " &integer'image(err_cnt);

You'd find that test cases 3 and test cases 4 increment err_cnt without failing:

reg_tb.vhdl:93:5:@30ns:(report note): err_cont = 0
reg_tb.vhdl:102:5:@50ns:(report note): err_cont = 0
reg_tb.vhdl:111:5:@70ns:(report note): err_cont = 1
reg_tb.vhdl:120:5:@90ns:(report note): err_cont = 2

The time stamps show these as test cases 1 - 4, err_cnt is a variable so it was incremented in the last two.

And that prevents the first report here:

    -- summary of all the tests
    if (err_cnt=0) then 
        assert false
        report "Testbench of register completely successfully!"
        severity note;
    else
        assert true
        report "Something wrong, check again pls!"
        severity error;
    end if;

As Brian commented the assert true is never false and you won't execute the second report statement in the summary.

As MbyD notes you have a disparity between what you are asserting and what you consider an error for err_cnt purposes and the if statement conditions are invalid for cases 3 and 4:

Answer 2

All of your reports are based on assertion, and if the assertion doesn't fail, the report will not be printed. Also, note that the assertion in each test is not the same as the condition to increment err_cnt, so you might fail multiple time without prints (as the assertion didn't fail) but still enter the "fail" part at the end, in which you'll get no print as assert true never fails.

Try adding the "report" and "severity" clauses into the relevant checks in the tests themselves, and see if anything gets printed. And also, remove the assertion in the final check, as you know (!) if the tests failed or not.

For example:

...
-- case 3
wait for 10 ns;
T_clear <= '0';                                        
wait for 10 ns;
if (T_Q/=T_I) then
    err_cnt := err_cnt+1;
    report "Test3 Failed!" severity error;
end if;

...

if (err_cnt=0) then 
    report "Testbench of register completely successfully!"
    severity note;
else
    report "Something wrong, check again pls!"
    severity error;
end if;