CODEWITHSUNDEEP
reportvhdl
SLP
SLP

Reputation: 315

Is there a way to print an assert only once at the beggining of a simulation in vhdl?

I have a vhdl entity which I instanciate in a testbench.

I would like it to print a report just once at the beginning of the simulation to show which generic was used.

Is that possible with synthetisable code ?

Thanks,

SLP

Upvotes: 0

Views: 260

Answers (1)

rascob
rascob

Reputation: 463

process
begin
    report "Integer parameter FOO value = " & integer'image(FOO);
    wait;
end process;

Caution on the wait; statement! As @user1155120 notes, processes without a sensitivity list will loop infinitely, unless stopped with a wait; statement.

Upvotes: 1

Related Questions