CODEWITHSUNDEEP
system-verilogassertionsuvmsystem-verilog-assertions
sarad
sarad

Reputation: 117

Where can I write concurrent assertion in monitor?

I have to write the following concurrent assertion in my monitor:

assert property (vif.cos == 1 |-> vif_out.y == vif.xi/sqrt(2));

I tried to put it in the run_phase, but I got the following error: Concurrent assertions are not allowed in tasks/class methods.

Where should I put it?

Upvotes: 0

Views: 1847

Answers (2)

AndresM
AndresM

Reputation: 1373

Please refer to the IEEE Std 1800-2012, Section 14.16 (Concurrent assertions).

A concurrent assertion statement may be specified in any of the following:

  • An always procedure or initial procedure as a statement, wherever these procedures may appear
  • A module
  • An interface
  • A program
  • A generate block
  • A checker

Personally, I would just move that piece of code into the interface file.

Upvotes: 1

Matthew
Matthew

Reputation: 13967

Concurrent assertions are not allowed in tasks/class methods. You have to put them in a module or similar (interface/program/checker).

Upvotes: 0

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