CODEWITHSUNDEEP
outputvhdlfpgapins
JohanPI
JohanPI

Reputation: 161

FPGA output pins outputting wrong state

I am writing a LCD controller for an FPGA and am having a really weird (for me at least) problem. The state machine that's supposed to output the needed bits to the screen misbehaves and gets the output pins "stuck" in an old state, while it clearly has moved on to later states.

Here is the relevant parts of the state machine:

PROCESS (clk)
  VARIABLE count: INTEGER RANGE 0 TO clk_divider; -- clk_divider is a generic positive.
BEGIN
 IF (clk'EVENT AND clk = '1') THEN
   count := count + 1;
   IF (count = clk_divider) THEN
     EAUX <= NOT EAUX;
     count := 0;
   END IF;
 END IF;
END PROCESS;

....

PROCESS (EAUX)
BEGIN
  IF (EAUX'EVENT AND EAUX = '1') THEN
    pr_state <= nx_state;
  END IF;
END PROCESS;

....

PROCESS (pr_state)
BEGIN
  CASE pr_state IS
    WHEN EntryMode => --6=1,7=Cursor increment/decrement, 8=Display shift on/off
      RSs <='0';
      DB(7 DOWNTO 0) := "00000110";
      nx_state <= WriteData;
    WHEN WriteData => --Write data to LCD:
      RSs <='1';
      YLED <= '1';
      DB(7 DOWNTO 0) := "01011111";
      i := i + 1;
      IF (i < chars) THEN
        nx_state <= WriteData;
      ELSE
        i := 0;
        nx_state <= ReturnHome;
      END IF;
    WHEN ReturnHome => --Return cursor
      RSs <='0';
      YLED <= '1';
      DB(7 DOWNTO 0) := "01011111";
      nx_state <= WriteData;
  END CASE;
END PROCESS;

Where the bits in the variable DB is assigned to the signal DBOUT:

DBOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- In entity
SHARED VARIABLE DB : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; -- In Architecture
DBOUT <= DB;

DBOUT is outputted (in the .ucf-file) as:

NET "DBOUT(0)" LOC = P10;
NET "DBOUT(1)" LOC = P11;
NET "DBOUT(2)" LOC = P12;
NET "DBOUT(3)" LOC = P13;
NET "DBOUT(4)" LOC = P15;
NET "DBOUT(5)" LOC = P16;
NET "DBOUT(6)" LOC = P18;
NET "DBOUT(7)" LOC = P19;

Using an oscilloscope on the pins I can see that it is clearly stuck outputting the "EntryMode" bits and the "RSs" is set at low, while the YLED (the internal led on the FPGA) is on (it's off at all other states). The really weird thing is (and this took a real long time to find) is that if I change the EntryMode bits from

"00000110"

to

"00000100"

it successfully passes the state and outputs the correct bits. It might be true for other changes as well, but I don't really feel like testing that too much. Any help or tips would be highly appreciated!

UPDATE: After popular request I explicitly put YLED to low in all the early states and switched (back) DB to be a signal. The result is that I can't reach the later states at all, or at least stay in them (even when fiddling with the magic bits, which I guess is a good thing) as the YLED only stays on for a split second after booting the FPGA.

Upvotes: 0

Views: 266

Answers (1)

VAP
VAP

Reputation: 551

There is a complete example, including theory, state machine, and VHDL code on pages 279-290 of "Finite State Machines in Hardware: Theory and Design...", by Volnei Pedroni, MIT Press, Dec. 2013.

Upvotes: 0

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