CODEWITHSUNDEEP
filterverilogramcoefficients
Suguresh Kumar Arali
Suguresh Kumar Arali

Reputation: 47

Verilog Code:FIR Filter= RAM modeling for reading coefficients values from file .. not showing simulation results

In verilog for only this line of code its showing simulation output

1) 

#( parameter width=1, length=16 )
       (* ram_style = "block" *)
          reg [(width)-1:0] mem[(1<<length)-1:0];

2)but for the below line it is not showing simulation output

  #( parameter width=8, length=16 )
   (* ram_style = "block" *)
         reg [(2*width)-1:0] mem[(1<<length)-1:0];

Explain why 2nd set of code is not showing simulation results? actually I want store 8 bits of min 65535 filter coefficients.. I want to read and write .. please guide me in this...

Upvotes: 1

Views: 677

Answers (1)

Morgan
Morgan

Reputation: 20514

A model of a RAM might look some thing like the code below, to write to it it is just a mater of sequencing the wr_addr, wr_data and wr_en.

module ram #(
  parameter DATA_W = 8,
  parameter DATA_D = 256
) (
  input                      clk,
  input                     rst_an,
  input  [0:$clog2(DATA_D)] rd_addr,
  input  [0:$clog2(DATA_D)] wr_addr,
  input  [0:DATA_W-1]       wr_data,
  input                     wr_en,
  output [0:DATA_W-1]       rd_data
);

reg [0:DATA_W-1] ram_data [0:DATA_D-1];

//READ
always @* begin
  rd_data = ram_data[rd_addr];
end

//WRITE
always @(posedge clk, negedge rst_an) begin
  if (~rst_an) begin
    for(int i = 0; i<DATA_D ; i++) begin
      ram_data[i]     <= 'b0 ;
    end 
  end
  else begin
    if (wr_en) begin
      ram_data[wr_addr] <= wr_data ;
    end
  end
end

for(int i = 0; i<DATA_D ; i++) is system verilog syntax.

for plain verilog declare integer i then replace the for loop with :

for(i = 0; i<DATA_D ; i=1+1)

clog2 : is used to get the address width required for the given depth.

If you want a depth of 4, you need 2 bits to address it. Depth of 16, 4 bits to address, ie

log2( 4) => 2
log2(16) => 4

If you use non-powers of two you want to round up or ceiling 

log2(5)  => 2.32192809489
clog2(5) => 3

Therefore clog2 is very useful to get the required addressing width from the depth of the RAM.

Upvotes: 1

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