CODEWITHSUNDEEP
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Suguresh Kumar Arali
Suguresh Kumar Arali

Reputation: 47

Stuck at synthesis for RAM block-> giving warning as Sourceless signal

Below is the RAM Module, where i wish to read the coefficients value. 

entermodule RAM_LP#( parameter width=8, length=16 )

(output reg [width*width-1:0]data_out,

input [width-1:0] address,

input clk,we);

// let the tools infer the right number of BRAMs

(* ram_style = "block" *)

(* synthesis, ram_block *)

reg [15:0] mem [0:65535];

parameter load_file = "generated/LP_coefficients.txt";

initial  
    begin
        $readmemh (load_file, mem);

end

 always @(posedge clk) begin

if (we) 

     data_out <= mem[address];
   end


endmodule

Giving warning and stuck at this point ->

WARNING:Xst:653 - Signal <mem> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.

Please guide me how to resolve this .

Upvotes: 0

Views: 214

Answers (1)

mcleod_ideafix
mcleod_ideafix

Reputation: 11418

You never write anything new to the RAM, so the symthesis tool warns you about this and treat this RAM as a ROM.

This portion of code:

always @(posedge clk) begin
  if (we) 
     data_out <= mem[address];
end

Reads current memory address when we is 1. I assume you want to write to the memory when we is 1, so it should be like this:

always @(posedge clk) begin
  if (we) 
     mem[address] <= data_in;
  data_out <= mem[address];
end

Being data_in an input port with data that you want to write into the memory. Note the clock cycle after the write operation, data_out will still have the old memory content. To have data_out to be updated if a write was performed, do like this:

always @(posedge clk) begin
  if (we) begin
     mem[address] <= data_in;
     data_out <= data_in;
  end
  else
    data_out <= mem[address];
end

Your module currently has no data_in port, so it describes a ROM, not a RAM, and in a ROM, this warning is harmless.

Upvotes: 1

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