CODEWITHSUNDEEP
verilog
Ali Eftekhariw
Ali Eftekhariw

Reputation: 41

How to fix the "Illegal reference to memory A" error

I created an 8-bit comparator, and I want to put it in testbench for simulation, but I have compile errors for testbench.

It is my module:

`include "BCS_RTL_VERILOG.v"
`timescale 1ns/1ns
module eight_bit_comparator(input [0:7] A, [0:7] B, E0, G0, output E8, G8);
wire [0:8] W1;
wire [0:8] W2;
assign W1[0] = E0;
assign W2[0] = G0;
genvar k;
generate
    for(k=0; k<8; k=k+1) begin: BCSgates
    RTL_BCS rtl_bcs(A[k], B[k], W1[k], W2[k], W1[k+1], W2[k+1]);
end
endgenerate
endmodule

and it is my testbench for my module with 6 error:

`timescale 1ns/1ns
module comp_eight_tb();
wire E_out, G_out;
reg A[0:7], B[0:7], E_in, G_in;
eight_bit_comparator(A, B, E_in, G_in, E_out, G_out);
initial begin
#25 A[0]=1;
#25 A[1]=1;
#25 A[2]=1;
#25 A[3]=1;
#25 A[4]=1;
#25 A[5]=1;
#25 A[6]=1;
#25 A[7]=1;
#0 B[0]=1;
#0 B[1]=1;
#0 B[2]=1;
#0 B[3]=1;
#0 B[4]=1;
#0 B[5]=1;
#0 B[6]=1;
#0 B[7]=1;
#5 E_in=1;
#0 G_in=1;
#20 $stop;
end
endmodule

errors:

comp_eight_tb.v(5): (vlog-2110) Illegal reference to memory "B".
comp_eight_tb.v(5): (vlog-2110) Illegal reference to net array "#implicit-wire#1".
comp_eight_tb.v(5): (vlog-2110) Illegal reference to memory "B".
comp_eight_tb.v(5): (vlog-2110) Illegal reference to memory "A".
comp_eight_tb.v(5): (vlog-2110) Illegal reference to net array "#implicit-wire#0".
comp_eight_tb.v(5): (vlog-2110) Illegal reference to memory "A".

These errors are for line 5 in testbench, but I couldn't recognize the problem. Can anyone solve this and explain why?

Upvotes: 1

Views: 2508

Answers (1)

toolic
toolic

Reputation: 62037

In the testbench, you should declare the bit range to the left of A and B. Also, it is more conventional to specify the MSB to the left of the LSB. Since you didn't post the code for the RTL_BCS module, I commented the instances of it out. This code compiles for me without errors:

module eight_bit_comparator (
    input [7:0] A,
    input [7:0] B,
    input E0,
    input G0,
    output E8,
    output G8
);
wire [0:8] W1;
wire [0:8] W2;
assign W1[0] = E0;
assign W2[0] = G0;
/*
genvar k;
generate
    for(k=0; k<8; k=k+1) begin: BCSgates
    RTL_BCS rtl_bcs(A[k], B[k], W1[k], W2[k], W1[k+1], W2[k+1]);
    end
endgenerate
*/
endmodule


`timescale 1ns/1ns
module comp_eight_tb();
wire E_out, G_out;
reg [7:0] A, B;
reg E_in, G_in;

eight_bit_comparator dut (A, B, E_in, G_in, E_out, G_out);

initial begin
    #25 A[0]=1;
    #25 A[1]=1;
    #25 A[2]=1;
    #25 A[3]=1;
    #25 A[4]=1;
    #25 A[5]=1;
    #25 A[6]=1;
    #25 A[7]=1;
    #0 B[0]=1;
    #0 B[1]=1;
    #0 B[2]=1;
    #0 B[3]=1;
    #0 B[4]=1;
    #0 B[5]=1;
    #0 B[6]=1;
    #0 B[7]=1;
    #5 E_in=1;
    #0 G_in=1;
    #20 $stop;
end
endmodule

I fixed another compile error by adding the dut instance name in the testbench.

Upvotes: 1

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