CODEWITHSUNDEEP
compiler-errorsvariable-assignmentverilog
Brahadeesh
Brahadeesh

Reputation: 2255

verilog assignment compiler error

I have a basic compiler error I am not able to figure out. Code:

module (input [127:0] in1,
        input [2:0] en);
real a1;
if(en==3'b001)
begin
  a1=$bitstoreal(in1[31:0]);
end

The error is :

Error: E:/Modeltech_pe_edu_10.0/examples/FloatingPt.v(20): near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER or '#' or '('

Upvotes: 1

Views: 17374

Answers (2)

Marty
Marty

Reputation: 6674

Assignments in Verilog are done by the assign statement if you're trying to set the value of a wire or within a procedural block (always or initial) for other data types.

In your example, you are missing an always block:

always @(*) begin
    if(en==3'b001) begin
        a1=$bitstoreal(in1[31:0]);
    end
end

You also might have a problem assigning a bus to the real type if you're not sure of what you're doing. You might need to write it as a1 = $itor(in1);

Upvotes: 3

user597225
user597225

Reputation:

You have procedural code outside a procedural construct. 

real a1;
initial
  begin
  if(en==3'b001)
    begin
    a1=$bitstoreal(in1[31:0]);
    end
  end

Upvotes: 3

Related Questions